iommu/arm-smmu: Clear cache lock bit of ACR

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According MMU-500r2 TRM, section 3.7.1 Auxiliary Control registers,
You can modify ACTLR only when the ACR.CACHE_LOCK bit is 0.

So before clearing ARM_MMU500_ACTLR_CPRE of each context bank,
need clear CACHE_LOCK bit of ACR register first.

Since CACHE_LOCK bit is only present in MMU-500r2 onwards,
need to check the major number of IDR7.

Reviewed-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>

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Peng Fan 2016-05-03 21:50:30 +08:00 • committed by Will Deacon

parent b7862e3559

commit 3ca3712a42

1 changed files with 22 additions and 1 deletions

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drivers/iommu/arm-smmu.c

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