net: phy: mscc: adding LCPLL reset to VSC8514

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At Power-On Reset, transients may cause the LCPLL to lock onto a
clock that is momentarily unstable. This is normally seen in QSGMII
setups where the higher speed 6G SerDes is being used.
This patch adds an initial LCPLL Reset to the PHY (first instance)
to avoid this issue.

Fixes: e4f9ba642f ("net: phy: mscc: add support for VSC8514 PHY.")
Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com>
Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

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This commit is contained in:

Bjarni Jonasson 2021-02-16 16:29:42 +01:00 • committed by David S. Miller

parent 455843d231

commit 3cc2c646be

2 changed files with 236 additions and 122 deletions

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8

drivers/net/phy/mscc/mscc.h

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350

drivers/net/phy/mscc/mscc_main.c

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