riscv: Add Zicclsm to cpufeature and hwprobe

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Zicclsm requires misaligned support for all regular load and store
instructions, both scalar and vector, but not AMOs or other
specialized forms of memory access, to main memory regions with both
the cacheability and coherence PMAs, as defined in the profiles spec.
Even though mandated, misaligned loads and stores might execute
extremely slowly. Standard software distributions should assume their
existence only for correctness, not for performance.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Andy Chiu <andy.chiu@sifive.com>
Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>
Tested-by: Charlie Jenkins <charlie@rivosinc.com>
Signed-off-by: Jesse Taube <jesse@rivosinc.com>
[andrew.jones: Rebased, rewrote doc text, minor commit message revisions]
Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
Signed-off-by: Guodong Xu <docular.xu@gmail.com>
Link: https://patch.msgid.link/20260701-rva23u64-hwprobe-v2-v5-5-2c61f94a695a@gmail.com
[pjw@kernel.org: updated to apply; added Andrew's username to his tag comments]
Signed-off-by: Paul Walmsley <pjw@kernel.org>

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This commit is contained in:

Jesse Taube 2026-08-07 19:24:33 -06:00 • committed by Paul Walmsley

parent fdef048705

commit 3cd63bc30c

5 changed files with 8 additions and 0 deletions

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4

Documentation/arch/riscv/hwprobe.rst

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arch/riscv/include/asm/hwcap.h

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arch/riscv/include/uapi/asm/hwprobe.h

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arch/riscv/kernel/cpufeature.c

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arch/riscv/kernel/sys_hwprobe.c

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