clk: tegra: Use correct parent for dpaux clock

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The dpaux clock is derived from pll_p_out0 (pll_p), not clk_m.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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Thierry Reding 2015-04-20 14:47:25 +02:00

parent 1ec7032ad5

commit 3d0f4e5f7a

1 changed files with 1 additions and 1 deletions

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drivers/clk/tegra/clk-tegra-periph.c

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