drm/amd/display: Programming correct VRR_EN bit in VTEM structure

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[Why]
In HDMI plugfest, MTK report our EMP with VRR_EN bit = 0.
VRR_EN bit is EMP-MD0-bit 0. Currently driver set 1 to bit 3.

[How]
Programming correct VRR_EN bit in EMP-MD0-bit0.

Signed-off-by: Hugo Hu <hugo.hu@amd.com>
Reviewed-by: Reza Amini <Reza.Amini@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

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Hugo Hu 2019-02-27 15:18:08 +08:00 • committed by Alex Deucher

parent 8db89b2e39

commit 3d5cc27231

1 changed files with 2 additions and 2 deletions

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drivers/gpu/drm/amd/display/modules/freesync/freesync.c

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