clk: tegra: change post IDDQ release delay to 5us

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Increase delay after PLL IDDQ release to 5us per PLL specifications.

based on work by Alex Frid <afrid@nvidia.com>

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

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Peter De Schrijver 2017-07-25 13:34:09 +03:00 • committed by Stephen Boyd

parent 82c875ca2b

commit 3dd065e70e

1 changed files with 1 additions and 1 deletions

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drivers/clk/tegra/clk-pll.c

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