From cb31bbfa4915455d9620974a1fbfb1a8f07b8903 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Fri, 9 Jul 2021 16:47:06 -0500 Subject: [PATCH 01/18] ARM: dts: am335x-boneblue: add gpio-line-names This adds gpio-line-names to the BeagleBone Blue DTS. The line names are based on the BeagleBone Blue rev A2 schematic. Signed-off-by: David Lechner Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-boneblue.dts | 143 +++++++++++++++++++++++++- 1 file changed, 142 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/am335x-boneblue.dts b/arch/arm/boot/dts/am335x-boneblue.dts index 0afcc2ee0b63..c6bb325ead33 100644 --- a/arch/arm/boot/dts/am335x-boneblue.dts +++ b/arch/arm/boot/dts/am335x-boneblue.dts @@ -435,12 +435,153 @@ &dcan1 { status = "okay"; }; +&gpio0 { + gpio-line-names = + "UART3_CTS", /* M17 */ + "UART3_RTS", /* M18 */ + "UART2_RX", /* A17 */ + "UART2_TX", /* B17 */ + "I2C1_SDA", /* B16 */ + "I2C1_SCL", /* A16 */ + "MMC0_CD", /* C15 */ + "SPI1_SS2", /* C18 */ + "EQEP_1A", /* V2 */ + "EQEP_1B", /* V3 */ + "MDIR_2B", /* V4 */ + "BATT_LED_2", /* T5 */ + "I2C2_SDA", /* D18 */ + "I2C2_SCL", /* D17 */ + "UART1_RX", /* D16 */ + "UART1_TX", /* D15 */ + "MMC2_DAT1", /* J18 */ + "MMC2_DAT2", /* K15 */ + "NC", /* F16 */ + "WIFI_LED", /* A15 */ + "MOT_STBY", /* D14 */ + "WLAN_IRQ", /* K16 */ + "PWM_2A", /* U10 */ + "PWM_2B", /* T10 */ + "", + "", + "BATT_LED_4", /* T11 */ + "BATT_LED_1", /* U12 */ + "BT_EN", /* K17 */ + "SPI1_SS1", /* H18 */ + "UART4_RX", /* T17 */ + "MDIR_1B"; /* U17 */ +}; + +&gpio1 { + gpio-line-names = + "MMC1_DAT0", /* U7 */ + "MMC1_DAT1", /* V7 */ + "MMC1_DAT2", /* R8 */ + "MMC1_DAT3", /* T8 */ + "MMC1_DAT4", /* U8 */ + "MMC1_DAT5", /* V8 */ + "MMC1_DAT6", /* R9 */ + "MMC1_DAT7", /* T9 */ + "DCAN1_TX", /* E18 */ + "DCAN1_RX", /* E17 */ + "UART0_RX", /* E15 */ + "UART0_TX", /* E16 */ + "EQEP_2A", /* T12 */ + "EQEP_2B", /* R12 */ + "PRU_E_A", /* V13 */ + "PRU_E_B", /* U13 */ + "MDIR_2A", /* R13 */ + "GPIO1_17", /* V14 */ + "PWM_1A", /* U14 */ + "PWM_1B", /* T14 */ + "EMMC_RST", /* R14 */ + "USR_LED_0", /* V15 */ + "USR_LED_1", /* U15 */ + "USR_LED_2", /* T15 */ + "USR_LED_3", /* V16 */ + "GPIO1_25", /* U16 */ + "MCASP0_AXR0", /* T16 */ + "MCASP0_AXR1", /* V17 */ + "MCASP0_ACLKR", /* U18 */ + "BATT_LED_3", /* V6 */ + "MMC1_CLK", /* U9 */ + "MMC1_CMD"; /* V9 */ +}; + +&gpio2 { + gpio-line-names = + "MDIR_1A", /* T13 */ + "MCASP0_FSR", /* V12 */ + "LED_RED", /* R7 */ + "LED_GREEN", /* T7 */ + "MODE_BTN", /* U6 */ + "PAUSE_BTN", /* T6 */ + "MDIR_4A", /* R1 */ + "MDIR_4B", /* R2 */ + "MDIR_3B", /* R3 */ + "MDIR_3A", /* R4 */ + "SVO7", /* T1 */ + "SVO8", /* T2 */ + "SVO5", /* T3 */ + "SVO6", /* T4 */ + "UART5_TX", /* U1 */ + "UART5_RX", /* U2 */ + "SERVO_EN", /* U3 */ + "NC", /* U4 */ + "UART3_RX", /* L17 */ + "UART3_TX", /* L16 */ + "MMC2_CLK", /* L15 */ + "DCAN1_SILENT", /* M16 */ + "SVO1", /* U5 */ + "SVO3", /* R5 */ + "SVO2", /* V5 */ + "SVO4", /* R6 */ + "MMC0_DAT3", /* F17 */ + "MMC0_DAT2", /* F18 */ + "MMC0_DAT1", /* G15 */ + "MMC0_DAT0", /* G16 */ + "MMC0_CLK", /* G17 */ + "MMC0_CMD"; /* G18 */ +}; + &gpio3 { + gpio-line-names = + "MMC2_DAT3", /* H16 */ + "GPIO3_1", /* H17 */ + "GPIO3_2", /* J15 */ + "MMC2_CMD", /* J16 */ + "MMC2_DAT0", /* J17 */ + "I2C0_SDA", /* C17 */ + "I2C0_SCL", /* C16 */ + "EMU1", /* C14 */ + "EMU0", /* B14 */ + "WL_EN", /* K18 */ + "WL_BT_OE", /* L18 */ + "", + "", + "NC", /* F15 */ + "SPI1_SCK", /* A13 */ + "SPI1_MISO", /* B13 */ + "SPI1_MOSI", /* D12 */ + "GPIO3_17", /* C12 */ + "EQEP_0A", /* B12 */ + "EQEP_0B", /* C13 */ + "GPIO3_20", /* D13 */ + "IMU_INT", /* A14 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + ""; + ls-buf-en-hog { gpio-hog; gpios = <10 GPIO_ACTIVE_HIGH>; output-high; - line-name = "LS_BUF_EN"; }; }; From 176f26bcd41a0ee8c69b14e97d1edf50e6485d52 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Thu, 15 Jul 2021 14:20:24 -0700 Subject: [PATCH 02/18] ARM: dts: Add support for dra762 abz package dra762 abz package is pin compatible with dra742 and few peripherals like DDR with upgraded speed. Add dt support for this SoC. Reported-by: Praneeth Bajjuri Tested-by: Praneeth Bajjuri Signed-off-by: Lokesh Vutla [khilman: forward port from ti-linux-5.4.y] Signed-off-by: Kevin Hilman Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am5748.dtsi | 6 +----- arch/arm/boot/dts/am574x-idk.dts | 4 ---- arch/arm/boot/dts/dra74x-p.dtsi | 27 +++++++++++++++++++++++++++ arch/arm/boot/dts/dra76x.dtsi | 12 ------------ 4 files changed, 28 insertions(+), 21 deletions(-) create mode 100644 arch/arm/boot/dts/dra74x-p.dtsi diff --git a/arch/arm/boot/dts/am5748.dtsi b/arch/arm/boot/dts/am5748.dtsi index 2cb577432766..c260aa1a85bd 100644 --- a/arch/arm/boot/dts/am5748.dtsi +++ b/arch/arm/boot/dts/am5748.dtsi @@ -3,7 +3,7 @@ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ */ -#include "dra76x.dtsi" +#include "dra74x-p.dtsi" #include "am57-pruss.dtsi" / { @@ -25,10 +25,6 @@ &usb3_tm { status = "disabled"; }; -&usb4_tm { - status = "disabled"; -}; - &atl_tm { status = "disabled"; }; diff --git a/arch/arm/boot/dts/am574x-idk.dts b/arch/arm/boot/dts/am574x-idk.dts index 1b8f3a28af05..dcc32f4b347f 100644 --- a/arch/arm/boot/dts/am574x-idk.dts +++ b/arch/arm/boot/dts/am574x-idk.dts @@ -36,10 +36,6 @@ &mmc2 { pinctrl-2 = <&mmc2_pins_default>; }; -&m_can0 { - status = "disabled"; -}; - &emif1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/dra74x-p.dtsi b/arch/arm/boot/dts/dra74x-p.dtsi new file mode 100644 index 000000000000..006189dad7a7 --- /dev/null +++ b/arch/arm/boot/dts/dra74x-p.dtsi @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "dra74x.dtsi" + +/ { + compatible = "ti,dra762", "ti,dra7"; + + ocp { + emif1: emif@4c000000 { + compatible = "ti,emif-dra7xx"; + reg = <0x4c000000 0x200>; + interrupts = ; + status = "disabled"; + }; + }; +}; + +/* MCAN interrupts are hard-wired to irqs 67, 68 */ +&crossbar_mpu { + ti,irqs-skip = <10 67 68 133 139 140>; +}; diff --git a/arch/arm/boot/dts/dra76x.dtsi b/arch/arm/boot/dts/dra76x.dtsi index a09e7bd77fc7..bc4ae91cba16 100644 --- a/arch/arm/boot/dts/dra76x.dtsi +++ b/arch/arm/boot/dts/dra76x.dtsi @@ -9,13 +9,6 @@ / { compatible = "ti,dra762", "ti,dra7"; ocp { - emif1: emif@4c000000 { - compatible = "ti,emif-dra7xx"; - reg = <0x4c000000 0x200>; - interrupts = ; - status = "disabled"; - }; - target-module@42c01900 { compatible = "ti,sysc-dra7-mcan", "ti,sysc"; ranges = <0x0 0x42c00000 0x2000>; @@ -90,11 +83,6 @@ csi2_1: port@1 { }; }; -/* MCAN interrupts are hard-wired to irqs 67, 68 */ -&crossbar_mpu { - ti,irqs-skip = <10 67 68 133 139 140>; -}; - &scm_conf_clocks { dpll_gmac_h14x2_ctrl_ck: dpll_gmac_h14x2_ctrl_ck@3fc { #clock-cells = <0>; From 591c091705e23b0d65d8ed592e877e7e49b7a495 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Sat, 17 Jul 2021 15:09:23 +0300 Subject: [PATCH 03/18] ARM: dts: omap4-l4-abe: Correct sidle modes for McASP McASP only supports Force-idle, No-idle and Smart-idle modes Signed-off-by: Peter Ujfalusi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4-l4-abe.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/omap4-l4-abe.dtsi b/arch/arm/boot/dts/omap4-l4-abe.dtsi index a9573d441dea..8287fdaa526e 100644 --- a/arch/arm/boot/dts/omap4-l4-abe.dtsi +++ b/arch/arm/boot/dts/omap4-l4-abe.dtsi @@ -192,8 +192,7 @@ target-module@28000 { /* 0x40128000, ap 8 08.0 */ reg-names = "rev", "sysc"; ti,sysc-sidle = , , - , - ; + ; /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ clocks = <&abe_clkctrl OMAP4_MCASP_CLKCTRL 0>; clock-names = "fck"; From ae3c05cf20efb0a2f3bfb92d23ebbe80a4b4dd24 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Sat, 17 Jul 2021 15:09:25 +0300 Subject: [PATCH 04/18] ARM: dts: omap4-l4-abe: Add McASP configuration OMAP4 has a single McASP instance with single serializer and locked for DIT mode. To be able to enable the support the following fixes needed: - Add the DAT port ranges to the target module's ranges We can already fill in the op-mode and serial-dir for McASP as it only supports this configuration, but keep the module disabled as there is no known device available where it is used. Signed-off-by: Peter Ujfalusi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4-l4-abe.dtsi | 35 ++++++++++++++++------------- 1 file changed, 19 insertions(+), 16 deletions(-) diff --git a/arch/arm/boot/dts/omap4-l4-abe.dtsi b/arch/arm/boot/dts/omap4-l4-abe.dtsi index 8287fdaa526e..7ae8b620515c 100644 --- a/arch/arm/boot/dts/omap4-l4-abe.dtsi +++ b/arch/arm/boot/dts/omap4-l4-abe.dtsi @@ -186,6 +186,7 @@ mcbsp3: mcbsp@0 { }; target-module@28000 { /* 0x40128000, ap 8 08.0 */ + /* 0x4012a000, ap 10 0a.0 */ compatible = "ti,sysc-mcasp", "ti,sysc"; reg = <0x28000 0x4>, <0x28004 0x4>; @@ -199,23 +200,25 @@ target-module@28000 { /* 0x40128000, ap 8 08.0 */ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x28000 0x1000>, - <0x49028000 0x49028000 0x1000>; - - /* - * Child device unsupported by davinci-mcasp. At least - * RX path is disabled for omap4, and only DIT mode - * works with no I2S. See also old Android kernel - * omap-mcasp driver for more information. - */ - }; - - target-module@2a000 { /* 0x4012a000, ap 10 0a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2a000 0x1000>, + <0x49028000 0x49028000 0x1000>, + <0x2000 0x2a000 0x1000>, <0x4902a000 0x4902a000 0x1000>; + + mcasp0: mcasp@0 { + compatible = "ti,omap4-mcasp-audio"; + reg = <0x0 0x2000>, + <0x4902a000 0x1000>; /* L3 data port */ + reg-names = "mpu","dat"; + interrupts = ; + interrupt-names = "tx"; + dmas = <&sdma 8>; + dma-names = "tx"; + clocks = <&abe_clkctrl OMAP4_MCASP_CLKCTRL 0>; + clock-names = "fck"; + op-mode = <1>; /* MCASP_DIT_MODE */ + serial-dir = < 1 >; /* 1 TX serializers */ + status = "disabled"; + }; }; target-module@2e000 { /* 0x4012e000, ap 12 0c.0 */ From feb29cf359fbb99098f953c14627970e972de415 Mon Sep 17 00:00:00 2001 From: Paul Barker Date: Tue, 20 Jul 2021 09:39:25 +0100 Subject: [PATCH 05/18] ARM: dts: am335x-boneblack: Extract HDMI config Move the HDMI hardware configuration for the BeagleBone Black out of the boneblack common dtsi file and into its own separate dtsi file. This allows the devicetree for BeagleBone Black derivatives which lack the hdmi encoding hardware to include the common dtsi file without needing to duplicate configuration or override the status of all hdmi-related nodes. Signed-off-by: Paul Barker Signed-off-by: Tony Lindgren --- .../arm/boot/dts/am335x-boneblack-common.dtsi | 135 ----------------- arch/arm/boot/dts/am335x-boneblack-hdmi.dtsi | 141 ++++++++++++++++++ .../boot/dts/am335x-boneblack-wireless.dts | 1 + arch/arm/boot/dts/am335x-boneblack.dts | 1 + arch/arm/boot/dts/am335x-sancloud-bbe.dts | 1 + 5 files changed, 144 insertions(+), 135 deletions(-) create mode 100644 arch/arm/boot/dts/am335x-boneblack-hdmi.dtsi diff --git a/arch/arm/boot/dts/am335x-boneblack-common.dtsi b/arch/arm/boot/dts/am335x-boneblack-common.dtsi index 64c3e9269f40..10494c4431b9 100644 --- a/arch/arm/boot/dts/am335x-boneblack-common.dtsi +++ b/arch/arm/boot/dts/am335x-boneblack-common.dtsi @@ -3,9 +3,6 @@ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ -#include -#include - &ldo3_reg { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -25,145 +22,13 @@ &mmc2 { non-removable; }; -&am33xx_pinmux { - nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - nxp_hdmi_bonelt_off_pins: nxp_hdmi_bonelt_off_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) - >; - }; - - mcasp0_pins: mcasp0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */ - AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/ - AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.GPIO1_27 */ - >; - }; -}; - -&lcdc { - status = "okay"; - - /* If you want to get 24 bit RGB and 16 BGR mode instead of - * current 16 bit RGB and 24 BGR modes, set the propety - * below to "crossed" and uncomment the video-ports -property - * in tda19988 node. - */ - blue-and-red-wiring = "straight"; - - port { - lcdc_0: endpoint@0 { - remote-endpoint = <&hdmi_0>; - }; - }; -}; - -&i2c0 { - tda19988: tda19988@70 { - compatible = "nxp,tda998x"; - reg = <0x70>; - nxp,calib-gpios = <&gpio1 25 0>; - interrupts-extended = <&gpio1 25 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-names = "default", "off"; - pinctrl-0 = <&nxp_hdmi_bonelt_pins>; - pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>; - - /* Convert 24bit BGR to RGB, e.g. cross red and blue wiring */ - /* video-ports = <0x234501>; */ - - #sound-dai-cells = <0>; - audio-ports = < TDA998x_I2S 0x03>; - - ports { - port@0 { - hdmi_0: endpoint@0 { - remote-endpoint = <&lcdc_0>; - }; - }; - }; - }; -}; - &rtc { system-power-controller; }; -&mcasp0 { - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&mcasp0_pins>; - status = "okay"; - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 0 0 1 0 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; -}; - / { memory@80000000 { device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512 MB */ }; - - clk_mcasp0_fixed: clk_mcasp0_fixed { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24576000>; - }; - - clk_mcasp0: clk_mcasp0 { - #clock-cells = <0>; - compatible = "gpio-gate-clock"; - clocks = <&clk_mcasp0_fixed>; - enable-gpios = <&gpio1 27 0>; /* BeagleBone Black Clk enable on GPIO1_27 */ - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "TI BeagleBone Black"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&dailink0_master>; - simple-audio-card,frame-master = <&dailink0_master>; - - dailink0_master: simple-audio-card,cpu { - sound-dai = <&mcasp0>; - clocks = <&clk_mcasp0>; - }; - - simple-audio-card,codec { - sound-dai = <&tda19988>; - }; - }; }; diff --git a/arch/arm/boot/dts/am335x-boneblack-hdmi.dtsi b/arch/arm/boot/dts/am335x-boneblack-hdmi.dtsi new file mode 100644 index 000000000000..7cfddada9348 --- /dev/null +++ b/arch/arm/boot/dts/am335x-boneblack-hdmi.dtsi @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include +#include + +&am33xx_pinmux { + nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; + + nxp_hdmi_bonelt_off_pins: nxp_hdmi_bonelt_off_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) + >; + }; + + mcasp0_pins: mcasp0_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/ + AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.GPIO1_27 */ + >; + }; +}; + +&lcdc { + status = "okay"; + + /* If you want to get 24 bit RGB and 16 BGR mode instead of + * current 16 bit RGB and 24 BGR modes, set the propety + * below to "crossed" and uncomment the video-ports -property + * in tda19988 node. + */ + blue-and-red-wiring = "straight"; + + port { + lcdc_0: endpoint@0 { + remote-endpoint = <&hdmi_0>; + }; + }; +}; + +&i2c0 { + tda19988: tda19988@70 { + compatible = "nxp,tda998x"; + reg = <0x70>; + nxp,calib-gpios = <&gpio1 25 0>; + interrupts-extended = <&gpio1 25 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default", "off"; + pinctrl-0 = <&nxp_hdmi_bonelt_pins>; + pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>; + + /* Convert 24bit BGR to RGB, e.g. cross red and blue wiring */ + /* video-ports = <0x234501>; */ + + #sound-dai-cells = <0>; + audio-ports = < TDA998x_I2S 0x03>; + + ports { + port@0 { + hdmi_0: endpoint@0 { + remote-endpoint = <&lcdc_0>; + }; + }; + }; + }; +}; + +&mcasp0 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mcasp0_pins>; + status = "okay"; + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 0 0 1 0 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; + +/ { + clk_mcasp0_fixed: clk_mcasp0_fixed { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24576000>; + }; + + clk_mcasp0: clk_mcasp0 { + #clock-cells = <0>; + compatible = "gpio-gate-clock"; + clocks = <&clk_mcasp0_fixed>; + enable-gpios = <&gpio1 27 0>; /* BeagleBone Black Clk enable on GPIO1_27 */ + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "TI BeagleBone Black"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink0_master>; + simple-audio-card,frame-master = <&dailink0_master>; + + dailink0_master: simple-audio-card,cpu { + sound-dai = <&mcasp0>; + clocks = <&clk_mcasp0>; + }; + + simple-audio-card,codec { + sound-dai = <&tda19988>; + }; + }; +}; diff --git a/arch/arm/boot/dts/am335x-boneblack-wireless.dts b/arch/arm/boot/dts/am335x-boneblack-wireless.dts index 80116646a3fe..8b2b24c80670 100644 --- a/arch/arm/boot/dts/am335x-boneblack-wireless.dts +++ b/arch/arm/boot/dts/am335x-boneblack-wireless.dts @@ -7,6 +7,7 @@ #include "am33xx.dtsi" #include "am335x-bone-common.dtsi" #include "am335x-boneblack-common.dtsi" +#include "am335x-boneblack-hdmi.dtsi" #include / { diff --git a/arch/arm/boot/dts/am335x-boneblack.dts b/arch/arm/boot/dts/am335x-boneblack.dts index e2ee8b8c07bc..9312197316f0 100644 --- a/arch/arm/boot/dts/am335x-boneblack.dts +++ b/arch/arm/boot/dts/am335x-boneblack.dts @@ -7,6 +7,7 @@ #include "am33xx.dtsi" #include "am335x-bone-common.dtsi" #include "am335x-boneblack-common.dtsi" +#include "am335x-boneblack-hdmi.dtsi" / { model = "TI AM335x BeagleBone Black"; diff --git a/arch/arm/boot/dts/am335x-sancloud-bbe.dts b/arch/arm/boot/dts/am335x-sancloud-bbe.dts index 275ba339adf4..c82295654bdd 100644 --- a/arch/arm/boot/dts/am335x-sancloud-bbe.dts +++ b/arch/arm/boot/dts/am335x-sancloud-bbe.dts @@ -7,6 +7,7 @@ #include "am33xx.dtsi" #include "am335x-bone-common.dtsi" #include "am335x-boneblack-common.dtsi" +#include "am335x-boneblack-hdmi.dtsi" #include / { From 3ed926537376a5b879d07e1dafd481acf4ba9d58 Mon Sep 17 00:00:00 2001 From: Paul Barker Date: Tue, 20 Jul 2021 09:39:26 +0100 Subject: [PATCH 06/18] ARM: dts: am335x-sancloud-bbe: Extract common code The Sancloud BBE, BBE Lite and BBE Extended+WiFi share a common hardware base so we can avoid duplication via a dtsi file. Signed-off-by: Paul Barker Signed-off-by: Tony Lindgren --- .../boot/dts/am335x-sancloud-bbe-common.dtsi | 96 +++++++++++++++++++ arch/arm/boot/dts/am335x-sancloud-bbe.dts | 91 +----------------- 2 files changed, 97 insertions(+), 90 deletions(-) create mode 100644 arch/arm/boot/dts/am335x-sancloud-bbe-common.dtsi diff --git a/arch/arm/boot/dts/am335x-sancloud-bbe-common.dtsi b/arch/arm/boot/dts/am335x-sancloud-bbe-common.dtsi new file mode 100644 index 000000000000..bd9c21813192 --- /dev/null +++ b/arch/arm/boot/dts/am335x-sancloud-bbe-common.dtsi @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&am33xx_pinmux { + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ + >; + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 1 reset value */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + /* MDIO reset value */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + }; + + usb_hub_ctrl: usb_hub_ctrl { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT_PULLUP, MUX_MODE7) /* rmii1_refclk.gpio0_29 */ + >; + }; +}; + +&mac { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + status = "okay"; +}; + +&davinci_mdio { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + status = "okay"; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&cpsw_emac0 { + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; +}; + +&i2c0 { + usb2512b: usb-hub@2c { + compatible = "microchip,usb2512b"; + reg = <0x2c>; + reset-gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; + /* wifi on port 4 */ + }; +}; diff --git a/arch/arm/boot/dts/am335x-sancloud-bbe.dts b/arch/arm/boot/dts/am335x-sancloud-bbe.dts index c82295654bdd..2a0ac9f5dda7 100644 --- a/arch/arm/boot/dts/am335x-sancloud-bbe.dts +++ b/arch/arm/boot/dts/am335x-sancloud-bbe.dts @@ -8,6 +8,7 @@ #include "am335x-bone-common.dtsi" #include "am335x-boneblack-common.dtsi" #include "am335x-boneblack-hdmi.dtsi" +#include "am335x-sancloud-bbe-common.dtsi" #include / { @@ -16,66 +17,6 @@ / { }; &am33xx_pinmux { - pinctrl-names = "default"; - - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ - >; - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - /* MDIO reset value */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - usb_hub_ctrl: usb_hub_ctrl { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT_PULLUP, MUX_MODE7) /* rmii1_refclk.gpio0_29 */ - >; - }; - mpu6050_pins: pinmux_mpu6050_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT, MUX_MODE7) /* uart0_ctsn.gpio1_8 */ @@ -89,29 +30,6 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE7) /* gpmc_a10.gpio1_ }; }; -&mac { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - status = "okay"; -}; - -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&cpsw_emac0 { - phy-handle = <ðphy0>; - phy-mode = "rgmii-id"; -}; - &i2c0 { lps331ap: barometer@5c { compatible = "st,lps331ap-press"; @@ -128,11 +46,4 @@ mpu6050: accelerometer@68 { interrupts = <2 IRQ_TYPE_EDGE_RISING>; orientation = <0xff 0 0 0 1 0 0 0 0xff>; }; - - usb2512b: usb-hub@2c { - compatible = "microchip,usb2512b"; - reg = <0x2c>; - reset-gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; - /* wifi on port 4 */ - }; }; From e48d54c1dfe7d99d4f030ebd0c60a6ba802ba465 Mon Sep 17 00:00:00 2001 From: Paul Barker Date: Tue, 20 Jul 2021 09:39:27 +0100 Subject: [PATCH 07/18] ARM: dts: am335x-sancloud-bbe-lite: New devicetree This adds support for the Sancloud BBE Lite which shares a common hardware base with the non-Lite version of the BBE. Signed-off-by: Paul Barker Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/Makefile | 1 + .../arm/boot/dts/am335x-sancloud-bbe-lite.dts | 50 +++++++++++++++++++ 2 files changed, 51 insertions(+) create mode 100644 arch/arm/boot/dts/am335x-sancloud-bbe-lite.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 863347b6b65e..8da525e7f0ab 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -843,6 +843,7 @@ dtb-$(CONFIG_SOC_AM33XX) += \ am335x-pocketbeagle.dtb \ am335x-regor-rdk.dtb \ am335x-sancloud-bbe.dtb \ + am335x-sancloud-bbe-lite.dtb \ am335x-shc.dtb \ am335x-sbc-t335.dtb \ am335x-sl50.dtb \ diff --git a/arch/arm/boot/dts/am335x-sancloud-bbe-lite.dts b/arch/arm/boot/dts/am335x-sancloud-bbe-lite.dts new file mode 100644 index 000000000000..d6ef19311a91 --- /dev/null +++ b/arch/arm/boot/dts/am335x-sancloud-bbe-lite.dts @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2021 SanCloud Ltd + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am335x-bone-common.dtsi" +#include "am335x-boneblack-common.dtsi" +#include "am335x-sancloud-bbe-common.dtsi" + +/ { + model = "SanCloud BeagleBone Enhanced Lite"; + compatible = "sancloud,am335x-boneenhanced", + "ti,am335x-bone-black", + "ti,am335x-bone", + "ti,am33xx"; +}; + +&am33xx_pinmux { + bb_spi0_pins: pinmux_bb_spi0_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT, MUX_MODE0) + >; + }; +}; + +&spi0 { + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&bb_spi0_pins>; + + channel@0 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "micron,spi-authenta"; + + reg = <0>; + spi-max-frequency = <16000000>; + spi-cpha; + }; +}; From 9b694bea4ba94efac1daddbfdef19a15a3518cd6 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Thu, 29 Jul 2021 17:46:11 -0500 Subject: [PATCH 08/18] ARM: dts: am33xx-l4: Add PRUSS node Add the DT nodes for the PRU-ICSS on AM33xx family of SoCs. The AM33xx SoCs contain a single PRU-ICSS instance and is represented by a pruss node and other child nodes. PRU-ICSS is supported only on AM3356+ SoCs though in the AM33xx family, so the nodes are added under the corresponding disabled interconnect target module node in the common am33xx-l4 dtsi file. The target module node should be enabled in only those derivative board files that use a SoC containing PRU-ICSS. The PRUSS subsystem node contains the entire address space. The various sub-modules of the PRU-ICSS are represented as individual child nodes (so platform devices themselves) of the PRUSS subsystem node. These include the two PRU cores and the interrupt controller. All the Data RAMs are represented within a child node of its own named 'memories' without any compatible. The Real Time Media Independent Interface controller (MII_RT), and the CFG sub-module are represented as syscon nodes. The PRUSS CFG module has a clock mux for IEP clock, this clk node is added under the CFG child node 'clocks'. The default source for this mux clock is the PRU_ICSS_IEP_GCLK clock. The DT nodes use all standard properties. The regs property in the PRU nodes define the addresses for the Instruction RAM, the Debug and Control sub-modules for that PRU core. The firmware for each PRU core is defined through a 'firmware-name' property. The default names for the firmware images for each PRU core are defined as follows (these can be adjusted either in derivative board dts files or through sysfs at runtime if required): PRU-ICSS PRU0 Core: am335x-pru1_0-fw PRU-ICSS PRU1 Core: am335x-pru1_1-fw Note: 1. There are few more sub-modules like the Industrial Ethernet Peripheral (IEP), MDIO, UART, eCAP that do not have bindings and so will be added in the future. 2. The PRUSS INTC on AM335x SoCs also connect the host interrupts 0 to TSC_ADC; 6 and 7 as possible DMA events, so use the 'ti,irqs-reserved' property in derivative board dts files _if_ any of them should not be handled by the host OS. Signed-off-by: Suman Anna Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am33xx-l4.dtsi | 71 ++++++++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi index 859e760df4c8..148176361b4e 100644 --- a/arch/arm/boot/dts/am33xx-l4.dtsi +++ b/arch/arm/boot/dts/am33xx-l4.dtsi @@ -853,6 +853,77 @@ pruss_tm: target-module@300000 { /* 0x4a300000, ap 9 04.0 */ #size-cells = <1>; ranges = <0x0 0x300000 0x80000>; status = "disabled"; + + pruss: pruss@0 { + compatible = "ti,am3356-pruss"; + reg = <0x0 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pruss_mem: memories@0 { + reg = <0x0 0x2000>, + <0x2000 0x2000>, + <0x10000 0x3000>; + reg-names = "dram0", "dram1", + "shrdram2"; + }; + + pruss_cfg: cfg@26000 { + compatible = "ti,pruss-cfg", "syscon"; + reg = <0x26000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x26000 0x2000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + pruss_iepclk_mux: iepclk-mux@30 { + reg = <0x30>; + #clock-cells = <0>; + clocks = <&l3_gclk>, /* icss_iep_gclk */ + <&pruss_ocp_gclk>; /* icss_ocp_gclk */ + }; + }; + }; + + pruss_mii_rt: mii-rt@32000 { + compatible = "ti,pruss-mii", "syscon"; + reg = <0x32000 0x58>; + }; + + pruss_intc: interrupt-controller@20000 { + compatible = "ti,pruss-intc"; + reg = <0x20000 0x2000>; + interrupts = <20 21 22 23 24 25 26 27>; + interrupt-names = "host_intr0", "host_intr1", + "host_intr2", "host_intr3", + "host_intr4", "host_intr5", + "host_intr6", "host_intr7"; + interrupt-controller; + #interrupt-cells = <3>; + }; + + pru0: pru@34000 { + compatible = "ti,am3356-pru"; + reg = <0x34000 0x2000>, + <0x22000 0x400>, + <0x22400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am335x-pru0-fw"; + }; + + pru1: pru@38000 { + compatible = "ti,am3356-pru"; + reg = <0x38000 0x2000>, + <0x24000 0x400>, + <0x24400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am335x-pru1-fw"; + }; + }; }; }; }; From 984ba7ee456b716e2667903686ad5ee944c249ba Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Thu, 29 Jul 2021 17:46:12 -0500 Subject: [PATCH 09/18] ARM: dts: am33xx-l4: Add PRUSS MDIO controller node The PRUSS on AM335x SoCs has a MDIO sub-module that can be used to control external PHYs associated with the Industrial Ethernet peripherals within the PRUSS. The MDIO module used within the PRU-ICSS is an instance of the MDIO Controller used in TI Davinci SoCs. The same bus frequency of 1 MHz is chosen as the regular MDIO node. The node is added to the common am33xx-l4.dtsi file and is disabled. This needs to be enabled in the respective board files using the relevant AM335x SoCs supporting PRUSS and where the ethernet is pinned out and connected properly. Signed-off-by: Suman Anna Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am33xx-l4.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi index 148176361b4e..c9629cb5ccd1 100644 --- a/arch/arm/boot/dts/am33xx-l4.dtsi +++ b/arch/arm/boot/dts/am33xx-l4.dtsi @@ -923,6 +923,17 @@ pru1: pru@38000 { reg-names = "iram", "control", "debug"; firmware-name = "am335x-pru1-fw"; }; + + pruss_mdio: mdio@32400 { + compatible = "ti,davinci_mdio"; + reg = <0x32400 0x90>; + clocks = <&dpll_core_m4_ck>; + clock-names = "fck"; + bus_freq = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; }; }; From 7c6a0fdcd4c2e5d6adfdf0e28d2bc89ffee7e73c Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Thu, 29 Jul 2021 17:46:13 -0500 Subject: [PATCH 10/18] ARM: dts: am335x-bone-common: Enable PRU-ICSS node The PRU-ICSS target module node was left in disabled state in the base am33xx-l4.dtsi file. Enable this node on all the AM335x beaglebone boards as they mostly use a AM3358 or a AM3359 SoC which do contain the PRU-ICSS IP. The PRUSS node and most of its child nodes are already enabled in the base dts file, and so become effective automatically with the enabling of this PRU-ICSS target-module node. The corresponding PRU nodes can be disabled later on if there are no use-cases defined to use a particular PRU core or the whole PRU-ICSS subsystem itself if both its PRU cores are unused. Signed-off-by: Suman Anna Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-bone-common.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi index 2d51d4bba6d4..34a0045b5f65 100644 --- a/arch/arm/boot/dts/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/am335x-bone-common.dtsi @@ -397,3 +397,7 @@ &rtc { clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; clock-names = "ext-clk", "int-clk"; }; + +&pruss_tm { + status = "okay"; +}; From 6bcf2b67e06ae40a84033d68c9f38c1586794f7d Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Thu, 29 Jul 2021 17:46:14 -0500 Subject: [PATCH 11/18] ARM: dts: am335x-evm: Enable PRU-ICSS module The PRU-ICSS target module node was left in disabled state in the base am33xx-l4.dtsi file. PRU-ICSS is supported on the AM335x EVM, so enable this node on the AM335x EVM. The PRUSS node and most of its child nodes are already enabled in the base dts file, and so become effective automatically with the enabling of this PRU-ICSS target module node. The corresponding PRU nodes can be disabled later on if there are no use-cases defined to use a particular PRU core or the whole PRU-ICSS subsystem itself if both its PRU cores are unused. Signed-off-by: Suman Anna Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-evm.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 9cf39c93defb..659e99eabe66 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -778,3 +778,7 @@ &rtc { clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; clock-names = "ext-clk", "int-clk"; }; + +&pruss_tm { + status = "okay"; +}; From 7acf5661b6a1298ff6489e343867e43fa48aac81 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Thu, 29 Jul 2021 17:46:15 -0500 Subject: [PATCH 12/18] ARM: dts: am335x-evmsk: Enable PRU-ICSS module The PRU-ICSS target module node was left in disabled state in the base am33xx-l4.dtsi file. PRU-ICSS is supported on the AM335x SK EVM board, so enable this node to support PRUSS on this board. The PRUSS node and most of its child nodes are already enabled in the base dts file, and so become effective automatically with the enabling of this PRU-ICSS target module node. The corresponding PRU nodes can be disabled later on if there are no use-cases defined to use a particular PRU core or the whole PRU-ICSS subsystem itself if both its PRU cores are unused. Signed-off-by: Suman Anna Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-evmsk.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index 001657be0381..a2db65538e51 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -715,3 +715,7 @@ &rtc { clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; clock-names = "ext-clk", "int-clk"; }; + +&pruss_tm { + status = "okay"; +}; From 8668711b00154b190dbb8f9ef5b3e189041f2b73 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Thu, 29 Jul 2021 17:46:16 -0500 Subject: [PATCH 13/18] ARM: dts: am335x-icev2: Enable PRU-ICSS module The PRU-ICSS target module node was left in disabled state in the base am33xx-l4.dtsi file. PRU-ICSS is supported on the AM335x ICEv2 board, so enable this node to support PRUSS on this board. The PRUSS node and most of its child nodes are already enabled in the base dts file, and so become effective automatically with the enabling of this PRU-ICSS target module node. The corresponding PRU nodes can be disabled later on if there are no use-cases defined to use a particular PRU core or the whole PRU-ICSS subsystem itself if both its PRU cores are unused. Signed-off-by: Suman Anna Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-icev2.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/am335x-icev2.dts b/arch/arm/boot/dts/am335x-icev2.dts index 5e598ac96dcc..e5ce89c8f54d 100644 --- a/arch/arm/boot/dts/am335x-icev2.dts +++ b/arch/arm/boot/dts/am335x-icev2.dts @@ -508,3 +508,7 @@ ethphy1: ethernet-phy@3 { reg = <3>; }; }; + +&pruss_tm { + status = "okay"; +}; From 152b53b41dc0ea48e3893ecccb13ba35bfbfce0d Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Thu, 29 Jul 2021 17:46:17 -0500 Subject: [PATCH 14/18] ARM: dts: am4372: Add the PRU-ICSS1 DT node Add the DT node for the PRU-ICSS1 instance on the AM437x family of SoCs. Each PRU-ICSS instance is represented by a pruss node and other child nodes. The nodes are added under the interconnect target module node in the common am4372 dtsi file. The PRU-ICSS instances are supported only on AM4376+ SoCs though in the AM437x family, so the interconnect target module node should be disabled in any derivative board dts file that uses AM4372 SoCs. The PRU-ICSS1 on AM437x is very similar to the PRUSS in AM33xx, except for variations in the RAM sizes, bus addresses and the number of interrupts coming into the MPU INTC (host interrupt 5 is routed to the other PRUSS instead of MPU). The PRUSS subsystem node contains the entire address space. The various sub-modules of the PRU-ICSS are represented as individual child nodes (so platform devices themselves) of the PRUSS subsystem node. These include the two PRU cores and the interrupt controller. All the Data RAMs are represented within a child node of its own named 'memories' without any compatible. The Real Time Media Independent Interface controller (MII_RT), and the CFG sub-module are represented as syscon nodes. The PRUSS CFG module has a clock mux for IEP clock, this clk node is added under the CFG child node 'clocks'. The default source for this mux clock is the PRU_ICSS_IEP_GCLK clock. The DT nodes use all standard properties. The regs property in the PRU nodes define the addresses for the Instruction RAM, the Debug and Control sub-modules for that PRU core. The firmware for each PRU core is defined through a 'firmware-name' property. The default names for the firmware images for each PRU core are defined as follows (these can be adjusted either in derivative board dts files or through sysfs at runtime if required): PRU-ICSS1 PRU0 Core: am437x-pru1_0-fw PRU-ICSS1 PRU1 Core: am437x-pru1_1-fw Note: 1. There are few more sub-modules like the Industrial Ethernet Peripheral (IEP), MDIO, UART, eCAP that do not have bindings and so will be added in the future. 2. The PRUSS INTC on AM437x SoCs also connect the host interrupt 0 to ADC0 and ADC1; 6 and 7 as possible DMA events, so use the 'ti,irqs-reserved' property in derivative board dts files _if_ any of them should not be handled by the host OS. Host interrupt 5 is already marked reserved as it is connected to the other PRUSS instance. Signed-off-by: Suman Anna Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am4372.dtsi | 78 +++++++++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index 57a85a6c34a2..ddfe58b1ae79 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -434,6 +434,84 @@ pruss_tm: target-module@54400000 { #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x54400000 0x80000>; + + pruss1: pruss@0 { + compatible = "ti,am4376-pruss1"; + reg = <0x0 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pruss1_mem: memories@0 { + reg = <0x0 0x2000>, + <0x2000 0x2000>, + <0x10000 0x8000>; + reg-names = "dram0", "dram1", + "shrdram2"; + }; + + pruss1_cfg: cfg@26000 { + compatible = "ti,pruss-cfg", "syscon"; + reg = <0x26000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x26000 0x2000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + pruss1_iepclk_mux: iepclk-mux@30 { + reg = <0x30>; + #clock-cells = <0>; + clocks = <&sysclk_div>, /* icss_iep_gclk */ + <&pruss_ocp_gclk>; /* icss_ocp_gclk */ + }; + }; + }; + + pruss1_mii_rt: mii-rt@32000 { + compatible = "ti,pruss-mii", "syscon"; + reg = <0x32000 0x58>; + }; + + pruss1_intc: interrupt-controller@20000 { + compatible = "ti,pruss-intc"; + reg = <0x20000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "host_intr0", "host_intr1", + "host_intr2", "host_intr3", + "host_intr4", + "host_intr6", "host_intr7"; + ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */ + }; + + pru1_0: pru@34000 { + compatible = "ti,am4376-pru"; + reg = <0x34000 0x3000>, + <0x22000 0x400>, + <0x22400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am437x-pru1_0-fw"; + }; + + pru1_1: pru@38000 { + compatible = "ti,am4376-pru"; + reg = <0x38000 0x3000>, + <0x24000 0x400>, + <0x24400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am437x-pru1_1-fw"; + }; + }; }; target-module@50000000 { From 0de8049ed4cb8c4a00fa3d7e60d8120148b42ff9 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Thu, 29 Jul 2021 17:46:18 -0500 Subject: [PATCH 15/18] ARM: dts: am4372: Add the PRU-ICSS0 DT node The AM4376+ SoCs have a second smaller PRU-ICSS subsystem (PRUSS0) in addition to the primary PRUSS1 instance. The PRUSS0 has less DRAM per PRU, and no Shared DRAM among other minor differences. The IEP and MII_RT modules even though present within the IP are not pinned out. This PRUSS0 instance has a weird SoC integration. It shares the same L3 OCP interconnect interface with PRUSS1, and also shares its reset line and clocks. Any external accesses from PRUSS0 requires the PRUSS1's PRUSS_SYSCFG register to be programmed properly. That said, it is its own IP instance (a cut-down version), and so it has been added as an independent node (sibling node to PRUSS1 node) and a child node of the corresponding PRUSS target module interconnect node. This allows the PRUSS0 instance to be enabled/disabled independently of the PRUSS1 instance. The nodes are added under the corresponding interconnect target module node in the common am4372 dtsi file. The PRU-ICSS instances are not supported on AM4372 SoC though in the AM437x family, so the interconnect target module node should be disabled in any derivative board dts file that uses AM4372 SoCs. The individual PRUSS node can be disabled in the corresponding board dts file if desired. The default names for the firmware images for each PRU core are defined as follows (these can be adjusted either in derivative board dts files or through sysfs at runtime if required): PRU-ICSS0 PRU0 Core: am437x-pru0_0-fw PRU-ICSS0 PRU1 Core: am437x-pru0_1-fw Note: 1. There are few more sub-modules like the Industrial Ethernet Peripheral (IEP), eCAP, UART, that do not have bindings and so will be added in the future. Only UART is pinned out, so others should be added in disabled state if added. 2. The PRUSS0 INTC on AM437x SoCs routes the host interrupt 5 to the other PRUSS1, so it is already marked reserved through the 'ti,irqs-reserved' property. Signed-off-by: Suman Anna Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am4372.dtsi | 77 +++++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index ddfe58b1ae79..2200a09c2065 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -512,6 +512,83 @@ pru1_1: pru@38000 { firmware-name = "am437x-pru1_1-fw"; }; }; + + pruss0: pruss@40000 { + compatible = "ti,am4376-pruss0"; + reg = <0x40000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pruss0_mem: memories@40000 { + reg = <0x40000 0x1000>, + <0x42000 0x1000>; + reg-names = "dram0", "dram1"; + }; + + pruss0_cfg: cfg@66000 { + compatible = "ti,pruss-cfg", "syscon"; + reg = <0x66000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x66000 0x2000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + pruss0_iepclk_mux: iepclk-mux@30 { + reg = <0x30>; + #clock-cells = <0>; + clocks = <&sysclk_div>, /* icss_iep_gclk */ + <&pruss_ocp_gclk>; /* icss_ocp_gclk */ + }; + }; + }; + + pruss0_mii_rt: mii-rt@72000 { + compatible = "ti,pruss-mii", "syscon"; + reg = <0x72000 0x58>; + status = "disabled"; + }; + + pruss0_intc: interrupt-controller@60000 { + compatible = "ti,pruss-intc"; + reg = <0x60000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "host_intr0", "host_intr1", + "host_intr2", "host_intr3", + "host_intr4", + "host_intr6", "host_intr7"; + ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */ + }; + + pru0_0: pru@74000 { + compatible = "ti,am4376-pru"; + reg = <0x74000 0x1000>, + <0x62000 0x400>, + <0x62400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am437x-pru0_0-fw"; + }; + + pru0_1: pru@78000 { + compatible = "ti,am4376-pru"; + reg = <0x78000 0x1000>, + <0x64000 0x400>, + <0x64400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am437x-pru0_1-fw"; + }; + }; }; target-module@50000000 { From 670be468b3f3177fe5e22fede270a7b158f0d7c6 Mon Sep 17 00:00:00 2001 From: "Andrew F. Davis" Date: Thu, 29 Jul 2021 17:46:19 -0500 Subject: [PATCH 16/18] ARM: dts: am4372: Add PRUSS MDIO controller node The PRU-ICSS1 instance on AM437x SoCs has a MDIO sub-module that can be used to control external PHYs associated with the Industrial Ethernet peripherals within the PRUSS. The MDIO module used within this PRU-ICSS is an instance of the MDIO Controller used in TI Davinci SoCs. The same bus frequency of 1 MHz is chosen as the regular MDIO node. Note that there is no MDIO node added to the smaller PRU-ICSS0 instance as the MDIO pins are not pinned out. The node is added and enabled in the common am4372.dtsi file by default, and disabled in all the existing AM437x board dts files. This node needs pinctrl lines, and so should be enabled only on boards where they are actually wired and pinned out for PRUSS Ethernet. Any new board dts file should disable these if they are not sure. Signed-off-by: Andrew F. Davis [s-anna@ti.com: fix reg address, add commit description] Signed-off-by: Suman Anna Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am4372.dtsi | 10 ++++++++++ arch/arm/boot/dts/am437x-cm-t43.dts | 4 ++++ arch/arm/boot/dts/am437x-gp-evm.dts | 4 ++++ arch/arm/boot/dts/am437x-idk-evm.dts | 4 ++++ arch/arm/boot/dts/am437x-sk-evm.dts | 4 ++++ arch/arm/boot/dts/am43x-epos-evm.dts | 4 ++++ 6 files changed, 30 insertions(+) diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index 2200a09c2065..61a1d88f9df6 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -511,6 +511,16 @@ pru1_1: pru@38000 { reg-names = "iram", "control", "debug"; firmware-name = "am437x-pru1_1-fw"; }; + + pruss1_mdio: mdio@32400 { + compatible = "ti,davinci_mdio"; + reg = <0x32400 0x90>; + clocks = <&dpll_core_m4_ck>; + clock-names = "fck"; + bus_freq = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; }; pruss0: pruss@40000 { diff --git a/arch/arm/boot/dts/am437x-cm-t43.dts b/arch/arm/boot/dts/am437x-cm-t43.dts index a83f46ed0c9a..5ce8e684e7d3 100644 --- a/arch/arm/boot/dts/am437x-cm-t43.dts +++ b/arch/arm/boot/dts/am437x-cm-t43.dts @@ -416,3 +416,7 @@ &cpu { <600000 1100000>, <300000 950000>; }; + +&pruss1_mdio { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index e2677682b540..c2e4896076e7 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -1118,3 +1118,7 @@ &rtc { &cpu { cpu0-supply = <&dcdc2>; }; + +&pruss1_mdio { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/am437x-idk-evm.dts b/arch/arm/boot/dts/am437x-idk-evm.dts index 2dc525512266..53f64e3ce735 100644 --- a/arch/arm/boot/dts/am437x-idk-evm.dts +++ b/arch/arm/boot/dts/am437x-idk-evm.dts @@ -537,3 +537,7 @@ opp100-600000000 { opp-suspend; }; }; + +&pruss1_mdio { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts index 496ed34f7755..20a34d2d85df 100644 --- a/arch/arm/boot/dts/am437x-sk-evm.dts +++ b/arch/arm/boot/dts/am437x-sk-evm.dts @@ -892,3 +892,7 @@ vpfe0_ep: endpoint { }; }; }; + +&pruss1_mdio { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index aae0af10a5b1..d16aa2221c91 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -1018,3 +1018,7 @@ &mux_synctimer32k_ck { &cpu { cpu0-supply = <&dcdc2>; }; + +&pruss1_mdio { + status = "disabled"; +}; From b8afeaee9d03f644f72b35e8433c9c2f651ade9c Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Thu, 29 Jul 2021 17:46:20 -0500 Subject: [PATCH 17/18] ARM: dts: am57xx: Add PRU-ICSS nodes Add the DT nodes for the PRU-ICSS1 and PRU-ICSS2 processor subsystems that are present on AM57xx family of SoCs. Each PRU-ICSS instance is represented by a pruss node and other child nodes. The two PRU-ICSSs are identical to each other. They are not supported on DRA7xx SoCs in general, so the nodes are added under the respective interconnect target module nodes in a common am57-pruss.dtsi file. The file is already included only in the AM57xx related board files. The PRU-ICSSs on AM57xx are very similar to the PRUSS in AM33xx and AM437x except for variations in the RAM sizes and the number of interrupts coming into the MPU INTC. The interrupt events into the PRU-ICSS also requires programming of the corresponding crossbars properly. The PRUSS subsystem node contains the entire address space. The various sub-modules of the PRU-ICSS are represented as individual child nodes (so platform devices themselves) of the PRUSS subsystem node. These include the two PRU cores and the interrupt controller. All the Data RAMs are represented within a child node of its own named 'memories' without any compatible. The Real Time Media Independent Interface controller (MII_RT), and the CFG sub-module are represented as syscon nodes. The PRUSS CFG module has a clock mux for IEP clock, this clk node is added under the CFG child node 'clocks'. The default source for this mux clock is the ICSS_IEP_CLK clock. The DT nodes use all standard properties. The regs property in the PRU nodes define the addresses for the Instruction RAM, the Debug and Control sub-modules for that PRU core. The firmware for each PRU core is defined through a 'firmware-name' property. The default names for the firmware images for each PRU core are defined as follows (these can be adjusted either in derivative board dts files or through sysfs at runtime if required): PRU-ICSS1 PRU0 Core: am57xx-pru1_0-fw PRU-ICSS1 PRU1 Core: am57xx-pru1_1-fw PRU-ICSS2 PRU0 Core: am57xx-pru2_0-fw PRU-ICSS2 PRU1 Core: am57xx-pru2_1-fw Note: 1. There are few more sub-modules like the Industrial Ethernet Peripheral (IEPs), MDIO, UART, eCAP that do not have bindings and so will be added in the future. 2. The PRUSS INTC on AM57xx SoCs also connect the host interrupts 6 and 7 as possible DMA events, so use the 'ti,irqs-reserved' property in derivative board dts files _if_ any of them should not be handled by the host OS. Signed-off-by: Suman Anna Signed-off-by: Roger Quadros Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am57-pruss.dtsi | 158 +++++++++++++++++++++++++++++- 1 file changed, 157 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/am57-pruss.dtsi b/arch/arm/boot/dts/am57-pruss.dtsi index 032c1acfcda3..494d56830b34 100644 --- a/arch/arm/boot/dts/am57-pruss.dtsi +++ b/arch/arm/boot/dts/am57-pruss.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ * * Common PRUSS data for TI AM57xx platforms */ @@ -25,6 +25,84 @@ pruss1_tm: target-module@4b226000 { #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x4b200000 0x80000>; + + pruss1: pruss@0 { + compatible = "ti,am5728-pruss"; + reg = <0x0 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pruss1_mem: memories@0 { + reg = <0x0 0x2000>, + <0x2000 0x2000>, + <0x10000 0x8000>; + reg-names = "dram0", "dram1", + "shrdram2"; + }; + + pruss1_cfg: cfg@26000 { + compatible = "ti,pruss-cfg", "syscon"; + reg = <0x26000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x26000 0x2000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + pruss1_iepclk_mux: iepclk-mux@30 { + reg = <0x30>; + #clock-cells = <0>; + clocks = <&dpll_gmac_m3x2_ck>, /* icss_iep_clk */ + <&dpll_gmac_h13x2_ck>; /* icss_clk */ + }; + }; + }; + + pruss1_mii_rt: mii-rt@32000 { + compatible = "ti,pruss-mii", "syscon"; + reg = <0x32000 0x58>; + }; + + pruss1_intc: interrupt-controller@20000 { + compatible = "ti,pruss-intc"; + reg = <0x20000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "host_intr0", "host_intr1", + "host_intr2", "host_intr3", + "host_intr4", "host_intr5", + "host_intr6", "host_intr7"; + }; + + pru1_0: pru@34000 { + compatible = "ti,am5728-pru"; + reg = <0x34000 0x3000>, + <0x22000 0x400>, + <0x22400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am57xx-pru1_0-fw"; + }; + + pru1_1: pru@38000 { + compatible = "ti,am5728-pru"; + reg = <0x38000 0x3000>, + <0x24000 0x400>, + <0x24400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am57xx-pru1_1-fw"; + }; + }; }; pruss2_tm: target-module@4b2a6000 { @@ -46,5 +124,83 @@ pruss2_tm: target-module@4b2a6000 { #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x4b280000 0x80000>; + + pruss2: pruss@0 { + compatible = "ti,am5728-pruss"; + reg = <0x0 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pruss2_mem: memories@0 { + reg = <0x0 0x2000>, + <0x2000 0x2000>, + <0x10000 0x8000>; + reg-names = "dram0", "dram1", + "shrdram2"; + }; + + pruss2_cfg: cfg@26000 { + compatible = "ti,pruss-cfg", "syscon"; + reg = <0x26000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x26000 0x2000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + pruss2_iepclk_mux: iepclk-mux@30 { + reg = <0x30>; + #clock-cells = <0>; + clocks = <&dpll_gmac_m3x2_ck>, /* icss_iep_clk */ + <&dpll_gmac_h13x2_ck>; /* icss_clk */ + }; + }; + }; + + pruss2_mii_rt: mii-rt@32000 { + compatible = "ti,pruss-mii", "syscon"; + reg = <0x32000 0x58>; + }; + + pruss2_intc: interrupt-controller@20000 { + compatible = "ti,pruss-intc"; + reg = <0x20000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "host_intr0", "host_intr1", + "host_intr2", "host_intr3", + "host_intr4", "host_intr5", + "host_intr6", "host_intr7"; + }; + + pru2_0: pru@34000 { + compatible = "ti,am5728-pru"; + reg = <0x34000 0x3000>, + <0x22000 0x400>, + <0x22400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am57xx-pru2_0-fw"; + }; + + pru2_1: pru@38000 { + compatible = "ti,am5728-pru"; + reg = <0x38000 0x3000>, + <0x24000 0x400>, + <0x24400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am57xx-pru2_1-fw"; + }; + }; }; }; From 8c054cd2818ea08555efe24a2ffde330833c2f3f Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Thu, 29 Jul 2021 17:46:21 -0500 Subject: [PATCH 18/18] ARM: dts: am57xx: Add PRUSS MDIO controller nodes The PRUSSs on AM57xx SoCs contain an MDIO controller that can be used to control external PHYs associated with the Industrial Ethernet peripherals within each PRUSS. The MDIO module used within the PRU-ICSS is an instance of the MDIO Controller used in TI Davinci SoCs. The same bus frequency of 1 MHz is chosen as the regular MDIO node. The nodes are added in the common am57-pruss.dtsi file and enabled by default, but are disabled in all the existing AM57xx board dts files. These nodes need pinctrl lines, and so should be enabled only on boards where they are actually wired and pinned out for PRUSS Ethernet. Any new board dts file should disable these if they are not sure. Signed-off-by: Suman Anna Signed-off-by: Andrew F. Davis Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am57-pruss.dtsi | 20 +++++++++++++++++++ arch/arm/boot/dts/am571x-idk.dts | 8 ++++++++ arch/arm/boot/dts/am572x-idk.dts | 8 ++++++++ arch/arm/boot/dts/am574x-idk.dts | 8 ++++++++ .../boot/dts/am57xx-beagle-x15-common.dtsi | 8 ++++++++ arch/arm/boot/dts/am57xx-cl-som-am57x.dts | 8 ++++++++ 6 files changed, 60 insertions(+) diff --git a/arch/arm/boot/dts/am57-pruss.dtsi b/arch/arm/boot/dts/am57-pruss.dtsi index 494d56830b34..46c5383f0eee 100644 --- a/arch/arm/boot/dts/am57-pruss.dtsi +++ b/arch/arm/boot/dts/am57-pruss.dtsi @@ -102,6 +102,16 @@ pru1_1: pru@38000 { reg-names = "iram", "control", "debug"; firmware-name = "am57xx-pru1_1-fw"; }; + + pruss1_mdio: mdio@32400 { + compatible = "ti,davinci_mdio"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&dpll_gmac_h13x2_ck>; + clock-names = "fck"; + bus_freq = <1000000>; + reg = <0x32400 0x90>; + }; }; }; @@ -201,6 +211,16 @@ pru2_1: pru@38000 { reg-names = "iram", "control", "debug"; firmware-name = "am57xx-pru2_1-fw"; }; + + pruss2_mdio: mdio@32400 { + compatible = "ti,davinci_mdio"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&dpll_gmac_h13x2_ck>; + clock-names = "fck"; + bus_freq = <1000000>; + reg = <0x32400 0x90>; + }; }; }; }; diff --git a/arch/arm/boot/dts/am571x-idk.dts b/arch/arm/boot/dts/am571x-idk.dts index e81078c2d00d..48425020281a 100644 --- a/arch/arm/boot/dts/am571x-idk.dts +++ b/arch/arm/boot/dts/am571x-idk.dts @@ -208,3 +208,11 @@ &mmc2 { pinctrl-1 = <&mmc2_pins_hs>; pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>; }; + +&pruss1_mdio { + status = "disabled"; +}; + +&pruss2_mdio { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/am572x-idk.dts b/arch/arm/boot/dts/am572x-idk.dts index 6504265f3f7e..94a738cb0a4d 100644 --- a/arch/arm/boot/dts/am572x-idk.dts +++ b/arch/arm/boot/dts/am572x-idk.dts @@ -27,3 +27,11 @@ &mmc2 { pinctrl-1 = <&mmc2_pins_hs>; pinctrl-2 = <&mmc2_pins_ddr_rev20>; }; + +&pruss1_mdio { + status = "disabled"; +}; + +&pruss2_mdio { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/am574x-idk.dts b/arch/arm/boot/dts/am574x-idk.dts index dcc32f4b347f..6dff3660bf09 100644 --- a/arch/arm/boot/dts/am574x-idk.dts +++ b/arch/arm/boot/dts/am574x-idk.dts @@ -39,3 +39,11 @@ &mmc2 { &emif1 { status = "okay"; }; + +&pruss1_mdio { + status = "disabled"; +}; + +&pruss2_mdio { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi index 6b82ecf803c5..994e69ab38d7 100644 --- a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi +++ b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi @@ -637,3 +637,11 @@ &dsp2 { status = "okay"; memory-region = <&dsp2_memory_region>; }; + +&pruss1_mdio { + status = "disabled"; +}; + +&pruss2_mdio { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts index aed81568a297..2e94f32d9dfc 100644 --- a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts +++ b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts @@ -618,3 +618,11 @@ &gpio2_target { status = "okay"; ti,no-reset-on-init; }; + +&pruss1_mdio { + status = "disabled"; +}; + +&pruss2_mdio { + status = "disabled"; +};