clk: rockchip: fix the incorrect pclk_edp div width for RK3399

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The range of the  pclk_edp_div_con is [13:8] and 6 bits, not 5.

Reported-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Tested-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

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Xing Zheng 2017-01-18 12:20:56 +08:00 • committed by Heiko Stuebner

parent 1a0abcd634

commit 3e1531dbc3

1 changed files with 1 additions and 1 deletions

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drivers/clk/rockchip/clk-rk3399.c

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