drm/i915: MCH_SSKPD is a 64 bit register on Haswell

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And the SNB_READ_WM0_LATENCY macro is not valid anymore because we
have the "New WM0" at 63:56, so the "Old WM0" could maybe be zero if
the new one is not zero.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

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Paulo Zanoni 2013-05-03 17:23:44 -03:00 • committed by Daniel Vetter

parent 85a02deb4c

commit 3e1f72664e

1 changed files with 1 additions and 1 deletions

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drivers/gpu/drm/i915/intel_pm.c

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