libnvdimm/nvdimm/flush: Allow architecture to override the flush barrier

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Architectures like ppc64 provide persistent memory specific barriers
that will ensure that all stores for which the modifications are
written to persistent storage by preceding dcbfps and dcbstps
instructions have updated persistent storage before any data
access or data transfer caused by subsequent instructions is initiated.
This is in addition to the ordering done by wmb()

Update nvdimm core such that architecture can use barriers other than
wmb to ensure all previous writes are architecturally visible for
the platform buffer flush.

Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200701072235.223558-5-aneesh.kumar@linux.ibm.com

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Aneesh Kumar K.V 2020-07-01 12:52:32 +05:30 • committed by Michael Ellerman

parent d358042793

commit 3e79f082eb

4 changed files with 29 additions and 5 deletions

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14

Documentation/memory-barriers.txt

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2

drivers/md/dm-writecache.c

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8

drivers/nvdimm/region_devs.c

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10

include/asm-generic/barrier.h

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