arm64: dts: socfpga: agilex5: Add L2 and L3 cache

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Add L2 and L3 cache nodes to the device tree to resolve the
"unable to detect cache hierarchy" warning reported by cacheinfo.

Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

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Adrian Ng Ho Yin 2025-10-15 10:12:42 +08:00 • committed by Dinh Nguyen

parent 2f6da95cfb

commit 3e99d51aaa

1 changed files with 18 additions and 0 deletions

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arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi

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