clk: at91: rework PLL rate calculation

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The AT91 PLL rate configuration is done by configuring a multiplier/divider
pair.
The previous calculation was over-complicated (and apparently buggy).
Simplify the implementation and add some comments to explain what is done
here.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Reported-by: Gaël PORTAY <gael.portay@gmail.com>
Tested-by: Gaël PORTAY <gael.portay@gmail.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

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Boris BREZILLON 2014-09-02 09:50:15 +02:00 • committed by Mike Turquette

parent 078a3eb519

commit 3ef9dd2bab

1 changed files with 77 additions and 70 deletions

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drivers/clk/at91/clk-pll.c

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