clk: renesas: rcar-gen3: Add custom clock for PLLs

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Currently the PLLs are modeled as fixed factor clocks, based on initial
settings.  However, enabling CPU boost clock rates requires increasing
the PLL clock rates.

Add a custom clock driver to model the PLL clocks.  This will allow the
Z (CPU) clock driver to request changing the PLL clock rate.

Based on a patch in the BSP by Takeshi Kihara
<takeshi.kihara.df@renesas.com>.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20210326120100.1577596-7-geert+renesas@glider.be

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This commit is contained in:

Geert Uytterhoeven 2021-03-26 13:00:59 +01:00

parent 50086045bd

commit 3f70795636

1 changed files with 128 additions and 19 deletions

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drivers/clk/renesas/rcar-gen3-cpg.c

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