From 3f8c7b2fdd0e8256b4b7a314e1dd4e1a35e7e9dd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Wed, 26 Aug 2026 16:40:22 +0300 Subject: [PATCH] drm/i915/cdclk: Do the DG2 CDCLK/pipe power well notify properly MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The pcode post notify needs to happen after the CDCLK has been changed, not before. Also move the pre_notify call a bit for the sake of symmetry. Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä Link: https://patch.msgid.link/20260826134033.13976-4-ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/display/intel_cdclk.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index f5b396c5955f..fea76ea806fe 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2850,9 +2850,6 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state) &new_cdclk_state->actual)) return; - if (display->platform.dg2) - intel_cdclk_pcode_pre_notify(state); - if (new_cdclk_state->disable_pipes) { cdclk_config = new_cdclk_state->actual; pipe = INVALID_PIPE; @@ -2877,6 +2874,9 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state) drm_WARN_ON(display->drm, !new_cdclk_state->base.changed); + if (display->platform.dg2) + intel_cdclk_pcode_pre_notify(state); + intel_set_cdclk(display, &cdclk_config, pipe, "Pre changing CDCLK to"); } @@ -2905,9 +2905,6 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state) &new_cdclk_state->actual)) return; - if (display->platform.dg2) - intel_cdclk_pcode_post_notify(state); - if (!new_cdclk_state->disable_pipes && new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk) pipe = new_cdclk_state->pipe; @@ -2918,6 +2915,9 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state) intel_set_cdclk(display, &new_cdclk_state->actual, pipe, "Post changing CDCLK to"); + + if (display->platform.dg2) + intel_cdclk_pcode_post_notify(state); } /* pixels per CDCLK */