drm/msm/a7xx: allow writing to CP_BV counter selection registers

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In addition to the CP_PERFCTR_CP_SEL register range, allow writes to the
CP_BV_PERFCTR_CP_SEL registers in the 0x8e0-0x8e6 range for profiling
purposes of tools like fdperf and perfetto.

Signed-off-by: Zan Dobersek <zdobersek@igalia.com>
Patchwork: https://patchwork.freedesktop.org/patch/580548/
[fixup a730_protect size]
Signed-off-by: Rob Clark <robdclark@chromium.org>

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Zan Dobersek 2024-02-29 08:49:11 +01:00 • committed by Rob Clark

parent 104e548a7c

commit 3f9bb601a1

1 changed files with 4 additions and 4 deletions

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8

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

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