drm/i915/gvt: add F_CMD_ACCESS flag for wa regs

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Instead of updating by MMIO write, all of the wa regs are initialized by
wa_ctx. From host side, it should make this behavior as expected, add
'F_CMD_ACCESS' flag to these regs and allow access by commands.

[  123.557608] gvt: vgpu 2: srm access to non-render register (b11c)
[  123.563728] gvt: vgpu 2: MI_STORE_REGISTER_MEM handler error
[  123.569409] gvt: vgpu 2: cmd parser error
[  123.573424] 0x0
[  123.573425] 0x24

[  123.578686] gvt: vgpu 2: scan workload error
[  123.582958] GVT Internal error  for the guest
[  123.587317] Now vgpu 2 will enter failsafe mode.
[  123.591938] gvt: vgpu 2: failed to submit desc 0
[  123.596557] gvt: vgpu 2: fail submit workload on ring 0
[  123.601786] gvt: vgpu 2: fail to emulate MMIO write 00002230 len 4

Acked-by: Yan Zhao <yan.y.zhao@intel.com>
Signed-off-by: Weinan Li <weinan.z.li@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>

...

This commit is contained in:

Weinan Li 2019-05-31 15:33:48 +08:00 • committed by Zhenyu Wang

parent 0b32e19749

commit 3fcb01f8ab

1 changed files with 7 additions and 6 deletions

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drivers/gpu/drm/i915/gvt/handlers.c

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