clk: tegra: Correct parent of the APBDMA clock

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APBDMA represents a clock gate to the APB DMA controller, the actual
clock source for the controller is PCLK.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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Dmitry Osipenko 2017-10-04 02:02:39 +03:00 • committed by Thierry Reding

parent 899f8095e6

commit 3ff46fd0b2

1 changed files with 1 additions and 1 deletions

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drivers/clk/tegra/clk-tegra-periph.c

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