powerpc/8xx: Drop special handling of Linear and IMMR mappings in I/D TLB handlers

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Up to now, linear and IMMR mappings are managed via huge TLB entries
through specific code directly in TLB miss handlers. This implies
some patching of the TLB miss handlers at startup, and a lot of
dedicated code.

Remove all this specific dedicated code.

For now we are back to normal handling via standard 4k pages. In the
next patches, linear memory mapping and IMMR mapping will be managed
through huge pages.

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/221b7e3ead80a5969629938c023f8cfe45fdd2fb.1589866984.git.christophe.leroy@csgroup.eu

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Christophe Leroy 2020-05-19 05:49:16 +00:00 • committed by Michael Ellerman

parent 684c1664e0

commit 400dc0f861

2 changed files with 3 additions and 129 deletions

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29

arch/powerpc/kernel/head_8xx.S

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103

arch/powerpc/mm/nohash/8xx.c

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