perf/x86/intel/uncore: Fix Intel SPR M3UPI event constraints

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SPR M3UPI have the exact same event constraints as ICX, so add the
constraints.

Fixes: 2a8e51eae7 ("perf/x86/intel/uncore: Add Sapphire Rapids server M3UPI support")
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/1629991963-102621-8-git-send-email-kan.liang@linux.intel.com

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Kan Liang 2021-08-26 08:32:43 -07:00 • committed by Peter Zijlstra

parent f01d7d558e

commit 4034fb207e

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arch/x86/events/intel/uncore_snbep.c

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