drm/i915/pvc: Annotate two more workaround/tuning registers as MCR

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XEHPC_LNCFMISCCFGREG0 and XEHPC_L3SCRUB are both in MCR register ranges
on PVC (with HALFBSLICE and L3BANK replication respectively), so they
should be explicitly declared as MCR registers and use MCR-aware
workaround handlers.

The workarounds/tuning settings should still be applied properly on PVC
even without the MCR annotation, but readback verification on
CONFIG_DRM_I915_DEBUG_GEM builds could potentitally give false positive
"workaround lost on load" warnings on parts fused such that a unicast
read targets a terminated register instance.

Fixes: a9e69428b1 ("drm/i915: Define MCR registers explicitly")
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230201222831.608281-1-matthew.d.roper@intel.com

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This commit is contained in:

Matt Roper 2023-02-01 14:28:28 -08:00

parent 9310dba467

commit 4039e44237

2 changed files with 12 additions and 6 deletions

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4

drivers/gpu/drm/i915/gt/intel_gt_regs.h

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14

drivers/gpu/drm/i915/gt/intel_workarounds.c

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