bus: ti-sysc: Assert reset only after disabling clocks

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The rstctrl reset must be asserted after gating the module clock as
described in the TRM at least for IVA. Otherwise the rstctrl reset
done with module clock enabled can hang the system.

Note that this issue is has been only seen with related IVA changes
that we do not currently have merged. So probably no need to apply
this patch as a fix.

Signed-off-by: Tony Lindgren <tony@atomide.com>

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This commit is contained in:

Tony Lindgren 2020-11-16 12:57:13 +02:00

parent c1995e5afa

commit 4097c9a64d

1 changed files with 13 additions and 11 deletions

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24

drivers/bus/ti-sysc.c

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