net: stmmac: socfpga: fix phy and ptp_ref setup for Arria10/Stratix10

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On the Arria10, Agilex, and Stratix10 SoC, there are a few differences from
the Cyclone5 and Arria5:
 - The emac PHY setup bits are in separate registers.
 - The PTP reference clock select mask is different.
 - The register to enable the emac signal from FPGA is different.

Thus, this patch creates a separate function for setting the phy modes on
Arria10/Agilex/Stratix10. The separation is based a new DTS binding:
"altr,socfpga-stmmac-a10-s10".

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>

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Dinh Nguyen 2019-06-05 10:05:51 -05:00 • committed by David S. Miller

parent b637e0856a

commit 40ae25505f

1 changed files with 104 additions and 13 deletions

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127

drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c

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