dpll: zl3073x: Specify phase adjustment granularity for pins

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[ Upstream commit 055a01b29f ]

Output pins phase adjustment values in the device are expressed
in half synth clock cycles. Use this number of cycles as output
pins' phase adjust granularity and simplify both get/set callbacks.

Reviewed-by: Michal Schmidt <mschmidt@redhat.com>
Reviewed-by: Petr Oros <poros@redhat.com>
Tested-by: Prathosh Satish <Prathosh.Satish@microchip.com>
Signed-off-by: Ivan Vecera <ivecera@redhat.com>
Reviewed-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
Link: https://patch.msgid.link/20251029153207.178448-3-ivecera@redhat.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Stable-dep-of: 5d41f95f5d ("dpll: zl3073x: Fix output pin phase adjustment sign")
Signed-off-by: Sasha Levin <sashal@kernel.org>

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This commit is contained in:

Ivan Vecera 2025-10-29 16:32:07 +01:00 • committed by Greg Kroah-Hartman

parent f399e8af18

commit 40bcd1fa0e

2 changed files with 25 additions and 44 deletions

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58

drivers/dpll/zl3073x/dpll.c

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11

drivers/dpll/zl3073x/prop.c

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