drm/radeon: Correct Transmit Margin masks

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Previously we masked PCIe Link Control 2 register values with "7 << 9",
which was apparently intended to be the Transmit Margin field, but instead
was the high order bit of Transmit Margin, the Enter Modified Compliance
bit, and the Compliance SOS bit.

Correct the mask to "7 << 7", which is the Transmit Margin field.

Link: https://lore.kernel.org/r/20191112173503.176611-3-helgaas@kernel.org
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

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This commit is contained in:

Bjorn Helgaas 2019-11-20 17:54:13 -06:00

parent 88027c89ea

commit 40bd4be5a6

2 changed files with 8 additions and 8 deletions

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8

drivers/gpu/drm/radeon/cik.c

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8

drivers/gpu/drm/radeon/si.c

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