net: dsa: mxl-gsw1xx: set SerDes NCO rate before SGMII reset

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gsw1xx_pcs_config() releases the SGMII shell from reset via
gsw1xx_pcs_reset() and only afterwards programs NCO_CTRL to select the
SerDes clock rate (1G NCO1 vs 2.5G NCO2). The chip boot loader uses the
other order: NCO_CTRL -> RST_REQ -> SGMII_PHY_HWBU_CTRL (GSW145 data
sheet, section 3.2.8, table 13).

Program NCO_CTRL before gsw1xx_pcs_reset() to follow that order. On an
Armada 7040 board driving a GSW145 whose switch comes up at 2.5G (pin strap
PS_SUBTYPE_MD[2] = 1, pin LED42 / PS1 bit 14; GSW145 data sheet tables 23
and 25), a 1 Gbps SGMII link only carried traffic with this change. It
matters when the rate the switch is left at - by the straps or by the boot
loader - differs from the rate the driver selects, which is likely why it
has not been seen before.

Cc: stable+noautosel@kernel.org # never worked
Signed-off-by: Jan Havran (Advantech Czech) <havran.jan@email.cz>
Reviewed-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Link: https://patch.msgid.link/20260907134818.16670-2-havran.jan@email.cz
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

...

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Jan Havran (Advantech Czech) 2026-09-07 15:48:16 +02:00 • committed by Jakub Kicinski

parent 10973152f2

commit 40c578ceae

1 changed files with 15 additions and 14 deletions

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drivers/net/dsa/lantiq/mxl-gsw1xx.c

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