clk: renesas: r8a779a0: Add the DU clock

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The DU clock is added to the S3D1 clock parent. The Renesas BSP lists
S2D1 as the clock parent, however there is no S2 clock on this platform.

S3D1 is chosen as a best effort guess and demonstrates functionality but
is not guaranteed to be correct.

Signed-off-by: Kieran Bingham <kieran.bingham@ideasonboard.com>
Link: https://lore.kernel.org/r/20210622232711.3219697-2-kieran.bingham@ideasonboard.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Kieran Bingham 2021-06-23 00:27:10 +01:00 • committed by Geert Uytterhoeven

parent d23fcff145

commit 417ed58dfc

1 changed files with 1 additions and 0 deletions

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drivers/clk/renesas/r8a779a0-cpg-mssr.c

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