CLK: HSDK: CGU: support PLL bypassing

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Support setting PLL to bypass mode to support output frequency
equal to input one.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Link: https://lkml.kernel.org/r/20200311134115.13257-3-Eugeniy.Paltsev@synopsys.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

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Eugeniy Paltsev 2020-03-11 16:41:14 +03:00 • committed by Stephen Boyd

parent 907f9291f9

commit 423f042a65

1 changed files with 34 additions and 27 deletions

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drivers/clk/clk-hsdk-pll.c

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