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RDMA/cxgb4: Use DSGLs for fastreg and adapter memory writes for T5.

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It enables direct DMA by HW to memory region PBL arrays and fast register PBL
arrays from host memory, vs the T4 way of passing these arrays in the WR itself.
The result is lower latency for memory registration, and larger PBL array
support for fast register operations.

This patch also updates ULP_TX_MEM_WRITE command fields for T5. Ordering bit of
ULP_TX_MEM_WRITE is at bit position 22 in T5 and at 23 in T4.

Signed-off-by: Vipul Pandya <vipul@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Vipul Pandya 2013-03-14 05:09:01 +00:00 • committed by David S. Miller
commit 42b6a94990
5 changed files with 190 additions and 36 deletions
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