perf/x86/intel: Update event constraints and cache_extra_regsfor NVL

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Update perf hard-coded event constraints and cache_extra_regs[] for
Novalake according to the latest NVL perfmon events.

The 4 PRECISE_OMR events (0xd4) are broken on Arcticwolf and would be
removed from upcoming released event list, so delete them from event
constraints and extra_regs array accordingly.

Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://patch.msgid.link/20260515061143.338553-10-dapeng1.mi@linux.intel.com

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Dapeng Mi 2026-05-15 14:11:41 +08:00 • committed by Peter Zijlstra

parent 65fd435095

commit 42f47511d9

3 changed files with 36 additions and 32 deletions

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55

arch/x86/events/intel/core.c

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11

arch/x86/events/intel/ds.c

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2

arch/x86/events/perf_event.h

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