PCI: Use DWORD accesses for LTR, L1 SS to avoid erratum

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Some devices have an erratum such that they only support DWORD accesses to
some registers.  E.g., this Bayhub O2 device ([VID:DID] = [0x1217:0x8621])
only supports DWORD accesses to LTR latency registers and L1 PM substates
control registers:

  https://github.com/rajatxjain/public_shared/blob/main/OZ711LV2_appnote.pdf

The L1 PM substate control registers are DWORD sized, and hence their
access in the kernel is already DWORD sized, so we don't need to do
anything for them.

However, the LTR registers being WORD sized, are in need of a solution.
Convert the WORD sized accesses to these registers into DWORD sized
accesses while saving and restoring them.

Link: https://lore.kernel.org/r/20211222012105.3438916-1-rajatja@google.com
Signed-off-by: Rajat Jain <rajatja@google.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

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Rajat Jain 2021-12-21 17:21:05 -08:00 • committed by Bjorn Helgaas

parent 0cf948aab9

commit 4353594eb0

2 changed files with 9 additions and 8 deletions

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16

drivers/pci/pci.c

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1

drivers/pci/pcie/aspm.c

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