x86/irq: Set up per host CPU posted interrupt descriptors

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To support posted MSIs, create a posted interrupt descriptor (PID) for each
host CPU. Later on, when setting up interrupt affinity, the IOMMU's
interrupt remapping table entry (IRTE) will point to the physical address
of the matching CPU's PID.

Each PID is initialized with the owner CPU's physical APICID as the
destination.

Originally-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/20240423174114.526704-7-jacob.jun.pan@linux.intel.com

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Jacob Pan 2024-04-23 10:41:08 -07:00 • committed by Thomas Gleixner

parent f5a3562ec9

commit 43650dcf6d

4 changed files with 35 additions and 0 deletions

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3

arch/x86/include/asm/hardirq.h

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6

arch/x86/include/asm/posted_intr.h

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3

arch/x86/kernel/cpu/common.c

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23

arch/x86/kernel/irq.c

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