ARM: l2c: add automatic enable of early BRESP

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The AXI bus protocol requires that a write response should only be
sent back to the master when the last write has been accepted.  Early
BRESP allows the L2C-310 to send the write response as soon as the
store buffer accepts the write address.

Cortex-A9 processors can signal to the L2C-310 that they wish to be
notified early, and if this optimisation is enabled, the L2C-310 can
signal an early write response.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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Russell King 2014-03-19 15:39:09 +00:00

parent ddf7d79bc7

commit 4374d64933

1 changed files with 22 additions and 3 deletions

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arch/arm/mm/cache-l2x0.c

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