iommu/tegra-smmu: Fix invalid ASID bits on Tegra30/114

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Both Tegra30 and Tegra114 have 4 ASID's and the corresponding bitfield of
the TLB_FLUSH register differs from later Tegra generations that have 128
ASID's.

In a result the PTE's are now flushed correctly from TLB and this fixes
problems with graphics (randomly failing tests) on Tegra30.

Cc: stable <stable@vger.kernel.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>

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Dmitry Osipenko 2019-03-07 01:50:07 +03:00 • committed by Joerg Roedel

parent 15ade5d2e7

commit 43a0541e31

1 changed files with 18 additions and 7 deletions

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drivers/iommu/tegra-smmu.c

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