drm/i915/mtl: Update cache coherency setting for context structure

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As context structure is shared memory for CPU/GPU, Wa_22016122933 is
needed for this memory block as well.

Signed-off-by: Zhanjun Dong <zhanjun.dong@intel.com>
CC: Fei Yang <fei.yang@intel.com>
Reviewed-by: Fei Yang <fei.yang@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230706174704.177929-1-zhanjun.dong@intel.com

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Zhanjun Dong 2023-07-06 10:47:04 -07:00 • committed by Daniele Ceraolo Spurio

parent 2f42c5afb3

commit 43aa755eae

1 changed files with 8 additions and 1 deletions

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9

drivers/gpu/drm/i915/gt/intel_lrc.c

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