clk: at91: clk-sam9x60-pll: re-factor to support plls with multiple outputs

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Some of the SAMA7G5 PLLs support multiple outputs (e.g. AUDIO PLL).
For these, split the PLL clock in two: fractional clock and
divider clock. In case PLLs supports multiple outputs (since these
outputs are dividers (with different settings) sharing the same
fractional part), it will register one fractional clock and multiple
divider clocks (dividers sharing the fractional clock).

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1595403506-8209-17-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

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Claudiu Beznea 2020-07-22 10:38:24 +03:00 • committed by Stephen Boyd

parent 0416824edc

commit 43b1bb4a9b

3 changed files with 433 additions and 186 deletions

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563

drivers/clk/at91/clk-sam9x60-pll.c

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22

drivers/clk/at91/pmc.h

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50

drivers/clk/at91/sam9x60.c

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