drm/msm/adreno: De-spaghettify the use of memory barriers

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Memory barriers help ensure instruction ordering, NOT time and order
of actual write arrival at other observers (e.g. memory-mapped IP).
On architectures employing weak memory ordering, the latter can be a
giant pain point, and it has been as part of this driver.

Moreover, the gpu_/gmu_ accessors already use non-relaxed versions of
readl/writel, which include r/w (respectively) barriers.

Replace the barriers with a readback (or drop altogether where possible)
that ensures the previous writes have exited the write buffer (as the CPU
must flush the write to the register it's trying to read back).

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/600869/
Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>

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Konrad Dybcio 2024-06-25 20:54:41 +02:00 • committed by Rob Clark

parent 1e210f462b

commit 43ec1a202c

2 changed files with 7 additions and 7 deletions

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4

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

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10

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

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