dt-bindings: clock: mediatek: Add mt8173 mfgtop

Browse source

The MFG (GPU) block on the MT8173 has a small glue layer, named MFG_TOP
in the datasheet, that contains clock gates, some power sequence signal
delays, and other unknown registers that get toggled when the GPU is
powered on.

The clock gates are exposed as clocks provided by a clock controller,
while the power sequencing bits are exposed as one singular power domain.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Brian Masney <bmasney@redhat.com>

...

This commit is contained in:

Chen-Yu Tsai 2026-07-28 17:17:59 +08:00 • committed by Brian Masney

parent 3ed463b69b

commit 442d24ce7f

2 changed files with 77 additions and 0 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

70

Documentation/devicetree/bindings/clock/mediatek,mt8173-mfgtop.yaml

View file

7

include/dt-bindings/clock/mt8173-clk.h

View file