phy: lynx-28g: make lynx_28g_set_lane_mode() more systematic

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The current approach of transitioning from one SerDes protocol to
another in lynx_28g_set_lane_mode() is too poetic.

Because the driver only supports 1GbE and 10GbE, it only modifies those
registers which it knows are different between these two modes. However,
that is hardly extensible for 25GbE, 40GbE, backplane modes, etc.

We need something more systematic to make sure that all lane and
protocol converter registers are written to consistent values, no matter
what was the source lane mode.

For that, we need to introduce tables with register field values, for
each supported lane mode.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Link: https://patch.msgid.link/20251125114847.804961-11-vladimir.oltean@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

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Vladimir Oltean 2025-11-25 13:48:42 +02:00 • committed by Vinod Koul

parent 6af3b6d365

commit 444bb9a7b3

1 changed files with 496 additions and 163 deletions

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drivers/phy/freescale/phy-fsl-lynx-28g.c

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