soc: xilinx: vcu: make pll post divider explicit

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According to the downstream driver documentation due to timing
constraints the output divider of the PLL has to be set to 1/2. Add a
helper function for that check instead of burying the code in one large
setup function.

The bit is undocumented and marked as reserved in the register
reference.

Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/20210121071659.1226489-10-m.tretter@pengutronix.de
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

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Michael Tretter 2021-01-21 08:16:53 +01:00 • committed by Stephen Boyd

parent 9c789deea2

commit 4472e1849d

1 changed files with 36 additions and 16 deletions

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drivers/soc/xilinx/xlnx_vcu.c

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