KVM: x86/mmu: Disable MMIO caching if MMIO value collides with L1TF

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Disable MMIO caching if the MMIO value collides with the L1TF mitigation
that usurps high PFN bits.  In practice this should never happen as only
CPUs with SME support can generate such a collision (because the MMIO
value can theoretically get adjusted into legal memory), and no CPUs
exist that support SME and are susceptible to L1TF.  But, closing the
hole is trivial.

Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20210225204749.1512652-5-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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Sean Christopherson 2021-02-25 12:47:29 -08:00 • committed by Paolo Bonzini

parent ec89e64386

commit 44aaa0150b

1 changed files with 12 additions and 1 deletions

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arch/x86/kvm/mmu/spte.c

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