From 9a71e89d0f9ebbca4f7b234a7f90f96224d04ec8 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 5 May 2022 19:43:53 +0100 Subject: [PATCH 01/27] arm64: dts: renesas: r9a07g043: Add ADC node Add ADC node to R9A07G043 (RZ/G2UL) SoC DTSI. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220505184353.512133-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index b31fb713ae4d..40201a16d653 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -483,8 +483,27 @@ }; adc: adc@10059000 { + compatible = "renesas,r9a07g043-adc", "renesas,rzg2l-adc"; reg = <0 0x10059000 0 0x400>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G043_ADC_ADCLK>, + <&cpg CPG_MOD R9A07G043_ADC_PCLK>; + clock-names = "adclk", "pclk"; + resets = <&cpg R9A07G043_ADC_PRESETN>, + <&cpg R9A07G043_ADC_ADRST_N>; + reset-names = "presetn", "adrst-n"; + power-domains = <&cpg>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + }; + channel@1 { + reg = <1>; + }; }; tsu: thermal@10059400 { From 7512af9f78dedea7e04225f665dad6750df7d095 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 11 May 2022 12:14:06 +0200 Subject: [PATCH 02/27] arm64: dts: renesas: beacon: Fix regulator node names Currently there are two nodes named "regulator_camera". This causes the former to be overwritten by the latter. Fix this by renaming them to unique names, using the preferred hyphen instead of an underscore. While at it, update the name of the audio regulator (which was added in the same commit) to use a hyphen. Fixes: a1d8a344f1ca0709 ("arm64: dts: renesas: Introduce r8a774a1-beacon-rzg2m-kit") Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/a9ac82bdf108162487289d091c53a9b3de393f13.1652263918.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi index 142e7ffbd2bd..63e7a39e100e 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi @@ -146,7 +146,7 @@ }; }; - reg_audio: regulator_audio { + reg_audio: regulator-audio { compatible = "regulator-fixed"; regulator-name = "audio-1.8V"; regulator-min-microvolt = <1800000>; @@ -174,7 +174,7 @@ vin-supply = <®_lcd>; }; - reg_cam0: regulator_camera { + reg_cam0: regulator-cam0 { compatible = "regulator-fixed"; regulator-name = "reg_cam0"; regulator-min-microvolt = <1800000>; @@ -183,7 +183,7 @@ enable-active-high; }; - reg_cam1: regulator_camera { + reg_cam1: regulator-cam1 { compatible = "regulator-fixed"; regulator-name = "reg_cam1"; regulator-min-microvolt = <1800000>; From 5cf12ac9493ae2603e5ba27c1040a88c7b26dd28 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 11 May 2022 12:24:59 +0200 Subject: [PATCH 03/27] arm64: dts: renesas: Rename numbered regulators Numbered regulators are prone to conflicts, causing silent overwrites (see e.g. [1]). Make conflicts less likely to happen by renaming all numbered regulators to names reflecting the regulator's purposes. [1] commit 45f5d5a9e34d3fe4 ("arm64: dts: renesas: r8a77995: draak: Fix backlight regulator name"). Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/b90dfeb834c4d7dabd22bf03396f33df58f54507.1652264651.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi | 4 ++-- arch/arm64/boot/dts/renesas/ebisu.dtsi | 6 +++--- arch/arm64/boot/dts/renesas/hihope-common.dtsi | 4 ++-- arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi | 4 ++-- arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi | 4 ++-- arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi | 4 ++-- arch/arm64/boot/dts/renesas/salvator-common.dtsi | 6 +++--- arch/arm64/boot/dts/renesas/ulcb.dtsi | 4 ++-- 8 files changed, 18 insertions(+), 18 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi index 877d076ffcc9..f5c1d74b738b 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi @@ -20,7 +20,7 @@ clock-output-names = "osc_32k"; }; - reg_1p8v: regulator0 { + reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; regulator-min-microvolt = <1800000>; @@ -29,7 +29,7 @@ regulator-always-on; }; - reg_3p3v: regulator1 { + reg_3p3v: regulator-3p3v { compatible = "regulator-fixed"; regulator-name = "fixed-3.3V"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm64/boot/dts/renesas/ebisu.dtsi b/arch/arm64/boot/dts/renesas/ebisu.dtsi index 72f359efa23e..9c311906fdaf 100644 --- a/arch/arm64/boot/dts/renesas/ebisu.dtsi +++ b/arch/arm64/boot/dts/renesas/ebisu.dtsi @@ -145,7 +145,7 @@ reg = <0x0 0x48000000 0x0 0x38000000>; }; - reg_1p8v: regulator0 { + reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; regulator-min-microvolt = <1800000>; @@ -154,7 +154,7 @@ regulator-always-on; }; - reg_3p3v: regulator1 { + reg_3p3v: regulator-3p3v { compatible = "regulator-fixed"; regulator-name = "fixed-3.3V"; regulator-min-microvolt = <3300000>; @@ -163,7 +163,7 @@ regulator-always-on; }; - reg_12p0v: regulator2 { + reg_12p0v: regulator-12p0v { compatible = "regulator-fixed"; regulator-name = "D12.0V"; regulator-min-microvolt = <12000000>; diff --git a/arch/arm64/boot/dts/renesas/hihope-common.dtsi b/arch/arm64/boot/dts/renesas/hihope-common.dtsi index 935d06515aa6..b062f41ee270 100644 --- a/arch/arm64/boot/dts/renesas/hihope-common.dtsi +++ b/arch/arm64/boot/dts/renesas/hihope-common.dtsi @@ -53,7 +53,7 @@ }; }; - reg_1p8v: regulator0 { + reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; regulator-min-microvolt = <1800000>; @@ -62,7 +62,7 @@ regulator-always-on; }; - reg_3p3v: regulator1 { + reg_3p3v: regulator-3p3v { compatible = "regulator-fixed"; regulator-name = "fixed-3.3V"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi index aeacd22e9eb0..9410796c8ad6 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi @@ -34,7 +34,7 @@ reg = <0x0 0x48000000 0x0 0x78000000>; }; - reg_1p8v: regulator0 { + reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; regulator-min-microvolt = <1800000>; @@ -43,7 +43,7 @@ regulator-always-on; }; - reg_3p3v: regulator1 { + reg_3p3v: regulator-3p3v { compatible = "regulator-fixed"; regulator-name = "fixed-3.3V"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi index 959a0ad1d367..78e6e2376b01 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi @@ -23,7 +23,7 @@ reg = <0x0 0x48000000 0x0 0x38000000>; }; - reg_1p8v: regulator0 { + reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; regulator-min-microvolt = <1800000>; @@ -32,7 +32,7 @@ regulator-always-on; }; - reg_3p3v: regulator1 { + reg_3p3v: regulator-3p3v { compatible = "regulator-fixed"; regulator-name = "fixed-3.3V"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi index a663115f5aae..429bdde579c3 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi @@ -24,7 +24,7 @@ reg = <0x0 0x48000000 0x0 0x38000000>; }; - reg_1p8v: regulator0 { + reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; regulator-min-microvolt = <1800000>; @@ -33,7 +33,7 @@ regulator-always-on; }; - reg_3p3v: regulator1 { + reg_3p3v: regulator-3p3v { compatible = "regulator-fixed"; regulator-name = "fixed-3.3V"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi index 31837fcd7bf0..aa44bef0c370 100644 --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi @@ -170,7 +170,7 @@ }; }; - reg_1p8v: regulator0 { + reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; regulator-min-microvolt = <1800000>; @@ -179,7 +179,7 @@ regulator-always-on; }; - reg_3p3v: regulator1 { + reg_3p3v: regulator-3p3v { compatible = "regulator-fixed"; regulator-name = "fixed-3.3V"; regulator-min-microvolt = <3300000>; @@ -188,7 +188,7 @@ regulator-always-on; }; - reg_12v: regulator2 { + reg_12v: regulator-12v { compatible = "regulator-fixed"; regulator-name = "fixed-12V"; regulator-min-microvolt = <12000000>; diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi index 90a4c0629d24..d5f0f75b249b 100644 --- a/arch/arm64/boot/dts/renesas/ulcb.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi @@ -76,7 +76,7 @@ }; }; - reg_1p8v: regulator0 { + reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; regulator-min-microvolt = <1800000>; @@ -85,7 +85,7 @@ regulator-always-on; }; - reg_3p3v: regulator1 { + reg_3p3v: regulator-3p3v { compatible = "regulator-fixed"; regulator-name = "fixed-3.3V"; regulator-min-microvolt = <3300000>; From 4872ca1f92b0545cd0898cf43fe0576fc7c7a1c7 Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Tue, 17 May 2022 09:16:44 +0100 Subject: [PATCH 04/27] arm64: dts: renesas: r9a09g011: Add ethernet nodes Add Ethernet nodes to SoC dtsi. Signed-off-by: Phil Edworthy Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220517081645.3764-2-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g011.dtsi | 51 ++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi index 27810f4ad4cb..d4cc5459fbb7 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi @@ -62,6 +62,57 @@ clock-names = "clk"; }; + avb: ethernet@a3300000 { + compatible = "renesas,etheravb-r9a09g011","renesas,etheravb-rzv2m"; + reg = <0 0xa3300000 0 0x800>; + interrupts = , /* ch0: Rx0 BE */ + , /* ch1: Rx1 NC */ + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , /* ch18: Tx0 BE */ + , /* ch19: Tx1 NC */ + , + , + , /* DiA */ + , /* DiB */ + , /* Line1_A */ + , /* Line1_B */ + , /* Line2_A */ + , /* Line2_B */ + ; /* Line3 MAC */ + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "dia", "dib", + "err_a", "err_b", "mgmt_a", "mgmt_b", + "line3"; + clocks = <&cpg CPG_MOD R9A09G011_ETH0_CLK_AXI>, + <&cpg CPG_MOD R9A09G011_ETH0_CLK_CHI>, + <&cpg CPG_MOD R9A09G011_ETH0_GPTP_EXT>; + clock-names = "axi", "chi", "gptp"; + resets = <&cpg R9A09G011_ETH0_RST_HW_N>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disable"; + }; + cpg: clock-controller@a3500000 { compatible = "renesas,r9a09g011-cpg"; reg = <0 0xa3500000 0 0x1000>; From dc24257124dba514164bd708dc1f4ca07538da00 Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Fri, 20 May 2022 11:07:36 +0100 Subject: [PATCH 05/27] arm64: dts: renesas: rzv2mevk2: Enable ethernet Enable Ethernet interface on RZ/V2M EVK. Signed-off-by: Phil Edworthy Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220520100736.15182-1-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts index c207d8ce5523..c3a52fa0b16e 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts @@ -14,6 +14,7 @@ aliases { serial0 = &uart0; + ethernet0 = &avb; }; chosen { @@ -35,6 +36,19 @@ }; }; +&avb { + renesas,no-ether-link; + phy-handle = <&phy0>; + phy-mode = "gmii"; + status = "okay"; + + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id001c.c916", + "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + &extal_clk { clock-frequency = <48000000>; }; From 5a3ad6f466fe7a187cbf4889d80a48606181c367 Mon Sep 17 00:00:00 2001 From: Linh Phung Date: Wed, 25 May 2022 17:13:55 +0200 Subject: [PATCH 06/27] arm64: dts: renesas: r8a779f0: Add thermal support Add support for 3 TSC nodes of thermal. The 4th node is for the control domain and not for Linux. Signed-off-by: Linh Phung [wsa: rebased, fixed resource size, removed unused 4th node breaking probe] Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20220525151355.24175-1-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 56 +++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index df46fb87cffc..a218ad28b133 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -157,6 +157,18 @@ #power-domain-cells = <1>; }; + tsc: thermal@e6198000 { + compatible = "renesas,r8a779f0-thermal"; + /* The 4th sensor is in control domain and not for Linux */ + reg = <0 0xe6198000 0 0x200>, + <0 0xe61a0000 0 0x200>, + <0 0xe61a8000 0 0x200>; + clocks = <&cpg CPG_MOD 919>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 919>; + #thermal-sensor-cells = <1>; + }; + i2c0: i2c@e6500000 { compatible = "renesas,i2c-r8a779f0", "renesas,rcar-gen4-i2c"; @@ -360,6 +372,50 @@ }; }; + thermal-zones { + sensor_thermal1: sensor1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 0>; + + trips { + sensor1_crit: sensor1-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + sensor_thermal2: sensor2-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 1>; + + trips { + sensor2_crit: sensor2-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + sensor_thermal3: sensor3-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 2>; + + trips { + sensor3_crit: sensor3-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, From 76f9a56152026c91adc33a6c1e49e8f5c0b80720 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 26 May 2022 22:42:31 +0200 Subject: [PATCH 07/27] arm64: dts: renesas: Adjust whitespace around '=' Fix whitespace coding style: use single space instead of tabs or multiple spaces around '=' sign in property assignment. No functional changes (same DTB). Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220526204231.832090-1-krzysztof.kozlowski@linaro.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/draak.dtsi | 2 +- arch/arm64/boot/dts/renesas/ebisu.dtsi | 2 +- arch/arm64/boot/dts/renesas/salvator-common.dtsi | 2 +- arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 14 +++++++------- arch/arm64/boot/dts/renesas/ulcb.dtsi | 2 +- 5 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/draak.dtsi b/arch/arm64/boot/dts/renesas/draak.dtsi index 7231f820d601..ef3bb835d5c0 100644 --- a/arch/arm64/boot/dts/renesas/draak.dtsi +++ b/arch/arm64/boot/dts/renesas/draak.dtsi @@ -630,7 +630,7 @@ bitclock-master = <&rsnd_for_ak4613>; frame-master = <&rsnd_for_ak4613>; playback = <&ssi3>, <&src5>, <&dvc0>; - capture = <&ssi4>, <&src6>, <&dvc1>; + capture = <&ssi4>, <&src6>, <&dvc1>; }; }; }; diff --git a/arch/arm64/boot/dts/renesas/ebisu.dtsi b/arch/arm64/boot/dts/renesas/ebisu.dtsi index 9c311906fdaf..8fc03491a11c 100644 --- a/arch/arm64/boot/dts/renesas/ebisu.dtsi +++ b/arch/arm64/boot/dts/renesas/ebisu.dtsi @@ -711,7 +711,7 @@ rcar_sound,dai { dai0 { playback = <&ssi0>, <&src0>, <&dvc0>; - capture = <&ssi1>, <&src1>, <&dvc1>; + capture = <&ssi1>, <&src1>, <&dvc1>; }; }; diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi index aa44bef0c370..b7c7911858b2 100644 --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi @@ -832,7 +832,7 @@ frame-master = <&rsnd_endpoint0>; playback = <&ssi0>, <&src0>, <&dvc0>; - capture = <&ssi1>, <&src1>, <&dvc1>; + capture = <&ssi1>, <&src1>, <&dvc1>; }; }; diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi index 5bcb84403ef6..408871c2859d 100644 --- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi @@ -206,12 +206,12 @@ clocks = <&clksndsel>; clock-names = "scki"; - VDD1-supply = <&snd_3p3v>; - VDD2-supply = <&snd_3p3v>; - VCCAD1-supply = <&snd_vcc5v>; - VCCAD2-supply = <&snd_vcc5v>; - VCCDA1-supply = <&snd_vcc5v>; - VCCDA2-supply = <&snd_vcc5v>; + VDD1-supply = <&snd_3p3v>; + VDD2-supply = <&snd_3p3v>; + VCCAD1-supply = <&snd_vcc5v>; + VCCAD2-supply = <&snd_vcc5v>; + VCCDA1-supply = <&snd_vcc5v>; + VCCDA2-supply = <&snd_vcc5v>; ports { #address-cells = <1>; @@ -438,7 +438,7 @@ bitclock-master; frame-master; dai-tdm-slot-num = <6>; - capture = <&ssi4>; + capture = <&ssi4>; }; }; }; diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi index d5f0f75b249b..0772dfe4adff 100644 --- a/arch/arm64/boot/dts/renesas/ulcb.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi @@ -411,7 +411,7 @@ bitclock-master; frame-master; playback = <&ssi0>, <&src0>, <&dvc0>; - capture = <&ssi1>, <&src1>, <&dvc1>; + capture = <&ssi1>, <&src1>, <&dvc1>; }; }; rsnd_port1: port@1 { From fd869e63b6ba16caf010cce5932bfd33dd680daa Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Mon, 30 May 2022 11:46:25 +0900 Subject: [PATCH 08/27] arm64: dts: renesas: r8a779f0: Add IPMMU nodes Add IPMMU nodes for r8a779f0. Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20220530024626.1870277-2-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 46 +++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index a218ad28b133..c16dbde8f76e 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -355,6 +355,52 @@ dma-channels = <16>; }; + ipmmu_rt0: iommu@ee480000 { + compatible = "renesas,ipmmu-r8a779f0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xee480000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm 10>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_rt1: iommu@ee4c0000 { + compatible = "renesas,ipmmu-r8a779f0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xee4c0000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm 19>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_ds0: iommu@eed00000 { + compatible = "renesas,ipmmu-r8a779f0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xeed00000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm 0>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_hc: iommu@eed40000 { + compatible = "renesas,ipmmu-r8a779f0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xeed40000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm 2>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_mm: iommu@eefc0000 { + compatible = "renesas,ipmmu-r8a779f0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xeefc0000 0 0x20000>; + interrupts = , + ; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + gic: interrupt-controller@f1000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; From 3a9747f0512409d366692caf5f05d5f0f5ab9d15 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Mon, 30 May 2022 11:46:26 +0900 Subject: [PATCH 09/27] arm64: dts: renesas: r8a779f0: Add iommus to DMAC nodes Add iommus properties to the DMAC nodes for r8a779f0. Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20220530024626.1870277-3-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index c16dbde8f76e..1a60a8e4b1bc 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -318,6 +318,14 @@ resets = <&cpg 709>; #dma-cells = <1>; dma-channels = <16>; + iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, + <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, + <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, + <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, + <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, + <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, + <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, + <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; }; dmac1: dma-controller@e7351000 { @@ -353,6 +361,14 @@ resets = <&cpg 710>; #dma-cells = <1>; dma-channels = <16>; + iommus = <&ipmmu_ds0 16>, <&ipmmu_ds0 17>, + <&ipmmu_ds0 18>, <&ipmmu_ds0 19>, + <&ipmmu_ds0 20>, <&ipmmu_ds0 21>, + <&ipmmu_ds0 22>, <&ipmmu_ds0 23>, + <&ipmmu_ds0 24>, <&ipmmu_ds0 25>, + <&ipmmu_ds0 26>, <&ipmmu_ds0 27>, + <&ipmmu_ds0 28>, <&ipmmu_ds0 29>, + <&ipmmu_ds0 30>, <&ipmmu_ds0 31>; }; ipmmu_rt0: iommu@ee480000 { From 5235d551779d2850d95ff1de762c69187fdf8dd5 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Fri, 3 Jun 2022 20:05:23 +0900 Subject: [PATCH 10/27] arm64: dts: renesas: r8a779f0: Add UFS node Add UFS node for R-Car S4-8 (r8a779f0). Signed-off-by: Yoshihiro Shimoda Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20220603110524.1997825-7-yoshihiro.shimoda.uh@renesas.com [geert: Move ufs30-clk to preserve sort order] Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index 1a60a8e4b1bc..54474ba18f5f 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -271,6 +271,18 @@ status = "disabled"; }; + ufs: ufs@e6860000 { + compatible = "renesas,r8a779f0-ufs"; + reg = <0 0xe6860000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 1514>, <&ufs30_clk>; + clock-names = "fck", "ref_clk"; + freq-table-hz = <200000000 200000000>, <38400000 38400000>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 1514>; + status = "disabled"; + }; + scif3: serial@e6c50000 { compatible = "renesas,scif-r8a779f0", "renesas,rcar-gen4-scif", "renesas,scif"; @@ -485,4 +497,11 @@ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; }; + + ufs30_clk: ufs30-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; }; From 290cedeca6fa315c54e056b7bdd3fdd99e5303eb Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Sat, 4 Jun 2022 01:29:40 +0200 Subject: [PATCH 11/27] arm64: dts: renesas: rzg2l-smarc: Use proper bool operator When checking for defined macros, we want the boolean AND not the binary one. Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20220603232940.21736-1-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi index aa170492dd2b..6be25a8a28db 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi @@ -29,7 +29,7 @@ #define SW_RSPI_CAN 1 #endif -#if (SW_SCIF_CAN & SW_RSPI_CAN) +#if (SW_SCIF_CAN && SW_RSPI_CAN) #error "Can not set 1 to both SW_SCIF_CAN and SW_RSPI_CAN due to HW routing" #endif From 9e8322dcf5f677cfc65d982546fb3aa6fa8b399a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= Date: Wed, 8 Jun 2022 11:08:50 +0200 Subject: [PATCH 12/27] ARM: dts: r9a06g032-rzn1d400-db: Enable rtc0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The RZ/N1D-DB board does have a battery to power the RTC. Enable the RTC device on this board. Signed-off-by: Clément Léger Link: https://lore.kernel.org/r/20220608090850.92735-1-clement.leger@bootlin.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts index 3f8f3ce87e12..ca39e1d681c1 100644 --- a/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts +++ b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts @@ -23,6 +23,10 @@ }; }; +&rtc0 { + status = "okay"; +}; + &uart0 { status = "okay"; }; From 650fd1d058a161a953f4034acae32471d4b94493 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 8 Jun 2022 17:16:25 +0200 Subject: [PATCH 13/27] arm64: dts: renesas: r8a779a0: Update to R-Car Gen4 compatible values Despite the name, R-Car V3U is the first member of the R-Car Gen4 family. Hence update the compatible properties in various device nodes to include family-specific compatible values for R-Car Gen4: - GPIO. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/b477eea0fc33a055d1b1874847e26614f68f5da0.1654701299.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 30 +++++++++++++++-------- 1 file changed, 20 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index b9731504b7cd..8162ef850376 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -105,7 +105,8 @@ }; gpio0: gpio@e6058180 { - compatible = "renesas,gpio-r8a779a0"; + compatible = "renesas,gpio-r8a779a0", + "renesas,rcar-gen4-gpio"; reg = <0 0xe6058180 0 0x54>; interrupts = ; clocks = <&cpg CPG_MOD 916>; @@ -119,7 +120,8 @@ }; gpio1: gpio@e6050180 { - compatible = "renesas,gpio-r8a779a0"; + compatible = "renesas,gpio-r8a779a0", + "renesas,rcar-gen4-gpio"; reg = <0 0xe6050180 0 0x54>; interrupts = ; clocks = <&cpg CPG_MOD 915>; @@ -133,7 +135,8 @@ }; gpio2: gpio@e6050980 { - compatible = "renesas,gpio-r8a779a0"; + compatible = "renesas,gpio-r8a779a0", + "renesas,rcar-gen4-gpio"; reg = <0 0xe6050980 0 0x54>; interrupts = ; clocks = <&cpg CPG_MOD 915>; @@ -147,7 +150,8 @@ }; gpio3: gpio@e6058980 { - compatible = "renesas,gpio-r8a779a0"; + compatible = "renesas,gpio-r8a779a0", + "renesas,rcar-gen4-gpio"; reg = <0 0xe6058980 0 0x54>; interrupts = ; clocks = <&cpg CPG_MOD 916>; @@ -161,7 +165,8 @@ }; gpio4: gpio@e6060180 { - compatible = "renesas,gpio-r8a779a0"; + compatible = "renesas,gpio-r8a779a0", + "renesas,rcar-gen4-gpio"; reg = <0 0xe6060180 0 0x54>; interrupts = ; clocks = <&cpg CPG_MOD 917>; @@ -175,7 +180,8 @@ }; gpio5: gpio@e6060980 { - compatible = "renesas,gpio-r8a779a0"; + compatible = "renesas,gpio-r8a779a0", + "renesas,rcar-gen4-gpio"; reg = <0 0xe6060980 0 0x54>; interrupts = ; clocks = <&cpg CPG_MOD 917>; @@ -189,7 +195,8 @@ }; gpio6: gpio@e6068180 { - compatible = "renesas,gpio-r8a779a0"; + compatible = "renesas,gpio-r8a779a0", + "renesas,rcar-gen4-gpio"; reg = <0 0xe6068180 0 0x54>; interrupts = ; clocks = <&cpg CPG_MOD 918>; @@ -203,7 +210,8 @@ }; gpio7: gpio@e6068980 { - compatible = "renesas,gpio-r8a779a0"; + compatible = "renesas,gpio-r8a779a0", + "renesas,rcar-gen4-gpio"; reg = <0 0xe6068980 0 0x54>; interrupts = ; clocks = <&cpg CPG_MOD 918>; @@ -217,7 +225,8 @@ }; gpio8: gpio@e6069180 { - compatible = "renesas,gpio-r8a779a0"; + compatible = "renesas,gpio-r8a779a0", + "renesas,rcar-gen4-gpio"; reg = <0 0xe6069180 0 0x54>; interrupts = ; clocks = <&cpg CPG_MOD 918>; @@ -231,7 +240,8 @@ }; gpio9: gpio@e6069980 { - compatible = "renesas,gpio-r8a779a0"; + compatible = "renesas,gpio-r8a779a0", + "renesas,rcar-gen4-gpio"; reg = <0 0xe6069980 0 0x54>; interrupts = ; clocks = <&cpg CPG_MOD 918>; From 06279f82da68882b83524385834eeacf1993724f Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 8 Jun 2022 17:17:42 +0200 Subject: [PATCH 14/27] arm64: dts: renesas: r8a779a0: Add CPU0 core clock Describe the clock for the first Cortex-A76 CPU core. For now no operating points are defined. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/3ace4eea4ff1cdc0f7b8ea7d0433c1063d795785.1654701400.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index 8162ef850376..3d668709d8a8 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -41,6 +41,7 @@ device_type = "cpu"; power-domains = <&sysc R8A779A0_PD_A1E0D0C0>; next-level-cache = <&L3_CA76_0>; + clocks = <&cpg CPG_CORE R8A779A0_CLK_Z0>; }; L3_CA76_0: cache-controller-0 { From ffeca49a8ba9aa39439d30b7bb51f453706b6a0d Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 8 Jun 2022 17:40:19 +0200 Subject: [PATCH 15/27] arm64: dts: renesas: r8a779f0: Add L3 cache controller Describe the cache configuration for the first Cortex-A55 CPU core on the Renesas R-Car S4-8 (R8A779F0) SoC. Extracted from a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven Reviewed-by: Yoshihiro Shimoda Tested-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/a63715ce1d2d2fcc7ab987f7a1b40847965e8d6a.1654701480.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index 54474ba18f5f..a268617587ea 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -23,6 +23,14 @@ reg = <0>; device_type = "cpu"; power-domains = <&sysc R8A779F0_PD_A1E0D0C0>; + next-level-cache = <&L3_CA55_0>; + }; + + L3_CA55_0: cache-controller-0 { + compatible = "cache"; + power-domains = <&sysc R8A779F0_PD_A2E0D0>; + cache-unified; + cache-level = <3>; }; }; From 2dcb78d2266c0a8790cc92af3cd08dadee3d7c27 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 8 Jun 2022 17:40:20 +0200 Subject: [PATCH 16/27] arm64: dts: renesas: r8a779f0: Add secondary CA55 CPU cores Complete the description of the Cortex-A55 CPU cores and L3 cache controllers on the Renesas R-Car S4-8 (R8A779F0) SoC, including CPU topology and PSCI support for enabling CPU cores. R-Car S4-8 has 8 Cortex-A55 cores, grouped in 4 clusters. Based on patches in the BSP by Takeshi Kihara. Signed-off-by: Geert Uytterhoeven Reviewed-by: Yoshihiro Shimoda Tested-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/d6af5975090d5830cb053b52400439bd1cbe8fc7.1654701480.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 138 +++++++++++++++++++++- 1 file changed, 133 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index a268617587ea..42347817a675 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -18,12 +18,114 @@ #address-cells = <1>; #size-cells = <0>; + cpu-map { + cluster0 { + core0 { + cpu = <&a55_0>; + }; + core1 { + cpu = <&a55_1>; + }; + }; + + cluster1 { + core0 { + cpu = <&a55_2>; + }; + core1 { + cpu = <&a55_3>; + }; + }; + + cluster2 { + core0 { + cpu = <&a55_4>; + }; + core1 { + cpu = <&a55_5>; + }; + }; + + cluster3 { + core0 { + cpu = <&a55_6>; + }; + core1 { + cpu = <&a55_7>; + }; + }; + }; + a55_0: cpu@0 { compatible = "arm,cortex-a55"; reg = <0>; device_type = "cpu"; power-domains = <&sysc R8A779F0_PD_A1E0D0C0>; next-level-cache = <&L3_CA55_0>; + enable-method = "psci"; + }; + + a55_1: cpu@100 { + compatible = "arm,cortex-a55"; + reg = <0x100>; + device_type = "cpu"; + power-domains = <&sysc R8A779F0_PD_A1E0D0C1>; + next-level-cache = <&L3_CA55_0>; + enable-method = "psci"; + }; + + a55_2: cpu@10000 { + compatible = "arm,cortex-a55"; + reg = <0x10000>; + device_type = "cpu"; + power-domains = <&sysc R8A779F0_PD_A1E0D1C0>; + next-level-cache = <&L3_CA55_1>; + enable-method = "psci"; + }; + + a55_3: cpu@10100 { + compatible = "arm,cortex-a55"; + reg = <0x10100>; + device_type = "cpu"; + power-domains = <&sysc R8A779F0_PD_A1E0D1C1>; + next-level-cache = <&L3_CA55_1>; + enable-method = "psci"; + }; + + a55_4: cpu@20000 { + compatible = "arm,cortex-a55"; + reg = <0x20000>; + device_type = "cpu"; + power-domains = <&sysc R8A779F0_PD_A1E1D0C0>; + next-level-cache = <&L3_CA55_2>; + enable-method = "psci"; + }; + + a55_5: cpu@20100 { + compatible = "arm,cortex-a55"; + reg = <0x20100>; + device_type = "cpu"; + power-domains = <&sysc R8A779F0_PD_A1E1D0C1>; + next-level-cache = <&L3_CA55_2>; + enable-method = "psci"; + }; + + a55_6: cpu@30000 { + compatible = "arm,cortex-a55"; + reg = <0x30000>; + device_type = "cpu"; + power-domains = <&sysc R8A779F0_PD_A1E1D1C0>; + next-level-cache = <&L3_CA55_3>; + enable-method = "psci"; + }; + + a55_7: cpu@30100 { + compatible = "arm,cortex-a55"; + reg = <0x30100>; + device_type = "cpu"; + power-domains = <&sysc R8A779F0_PD_A1E1D1C1>; + next-level-cache = <&L3_CA55_3>; + enable-method = "psci"; }; L3_CA55_0: cache-controller-0 { @@ -32,6 +134,27 @@ cache-unified; cache-level = <3>; }; + + L3_CA55_1: cache-controller-1 { + compatible = "cache"; + power-domains = <&sysc R8A779F0_PD_A2E0D1>; + cache-unified; + cache-level = <3>; + }; + + L3_CA55_2: cache-controller-2 { + compatible = "cache"; + power-domains = <&sysc R8A779F0_PD_A2E1D0>; + cache-unified; + cache-level = <3>; + }; + + L3_CA55_3: cache-controller-3 { + compatible = "cache"; + power-domains = <&sysc R8A779F0_PD_A2E1D1>; + cache-unified; + cache-level = <3>; + }; }; extal_clk: extal { @@ -53,6 +176,11 @@ interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; }; + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + /* External SCIF clock - to be overridden by boards that provide it */ scif_clk: scif { compatible = "fixed-clock"; @@ -445,7 +573,7 @@ reg = <0x0 0xf1000000 0 0x20000>, <0x0 0xf1060000 0 0x110000>; interrupts = ; + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; }; prr: chipid@fff00044 { @@ -500,10 +628,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; }; ufs30_clk: ufs30-clk { From 9bc7cd07aadedaa388636fe15966bea5e3f91ea7 Mon Sep 17 00:00:00 2001 From: Tho Vu Date: Wed, 8 Jun 2022 17:40:21 +0200 Subject: [PATCH 17/27] arm64: dts: renesas: r8a779f0: Add CPUIdle support Support CPUIdle for ARM Cortex-A55 on R-Car S4-8. Signed-off-by: Tho Vu Signed-off-by: Geert Uytterhoeven Reviewed-by: Yoshihiro Shimoda Tested-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/5310792ce4c06515a5373ff44ceb9b925f007489.1654701480.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index 42347817a675..8e612eb35b30 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -63,6 +63,7 @@ power-domains = <&sysc R8A779F0_PD_A1E0D0C0>; next-level-cache = <&L3_CA55_0>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; }; a55_1: cpu@100 { @@ -72,6 +73,7 @@ power-domains = <&sysc R8A779F0_PD_A1E0D0C1>; next-level-cache = <&L3_CA55_0>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; }; a55_2: cpu@10000 { @@ -81,6 +83,7 @@ power-domains = <&sysc R8A779F0_PD_A1E0D1C0>; next-level-cache = <&L3_CA55_1>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; }; a55_3: cpu@10100 { @@ -90,6 +93,7 @@ power-domains = <&sysc R8A779F0_PD_A1E0D1C1>; next-level-cache = <&L3_CA55_1>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; }; a55_4: cpu@20000 { @@ -99,6 +103,7 @@ power-domains = <&sysc R8A779F0_PD_A1E1D0C0>; next-level-cache = <&L3_CA55_2>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; }; a55_5: cpu@20100 { @@ -108,6 +113,7 @@ power-domains = <&sysc R8A779F0_PD_A1E1D0C1>; next-level-cache = <&L3_CA55_2>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; }; a55_6: cpu@30000 { @@ -117,6 +123,7 @@ power-domains = <&sysc R8A779F0_PD_A1E1D1C0>; next-level-cache = <&L3_CA55_3>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; }; a55_7: cpu@30100 { @@ -126,6 +133,7 @@ power-domains = <&sysc R8A779F0_PD_A1E1D1C1>; next-level-cache = <&L3_CA55_3>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; }; L3_CA55_0: cache-controller-0 { @@ -155,6 +163,19 @@ cache-unified; cache-level = <3>; }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <400>; + exit-latency-us = <500>; + min-residency-us = <4000>; + }; + }; }; extal_clk: extal { From e5fba0bc8240eb3f255e1f2cd5c74ecd29363791 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 8 Jun 2022 17:40:22 +0200 Subject: [PATCH 18/27] arm64: dts: renesas: r8a779f0: Add CPU core clocks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Describe the clocks for the eight Cortex-A55 CPU cores. CA55 Sub-System 0 (first 2 clusters / CPU cores 0-3) is clocked by Z0φ. CA55 Sub-System 1 (last 2 clusters / CPU cores 4-7) is clocked by Z1φ. For now no operating points are defined. Signed-off-by: Geert Uytterhoeven Reviewed-by: Yoshihiro Shimoda Tested-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/c502087f9affa86dd665def0d990d277a51cc75c.1654701480.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index 8e612eb35b30..907984d2b81e 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -64,6 +64,7 @@ next-level-cache = <&L3_CA55_0>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; }; a55_1: cpu@100 { @@ -74,6 +75,7 @@ next-level-cache = <&L3_CA55_0>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; }; a55_2: cpu@10000 { @@ -84,6 +86,7 @@ next-level-cache = <&L3_CA55_1>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; }; a55_3: cpu@10100 { @@ -94,6 +97,7 @@ next-level-cache = <&L3_CA55_1>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; }; a55_4: cpu@20000 { @@ -104,6 +108,7 @@ next-level-cache = <&L3_CA55_2>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; }; a55_5: cpu@20100 { @@ -114,6 +119,7 @@ next-level-cache = <&L3_CA55_2>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; }; a55_6: cpu@30000 { @@ -124,6 +130,7 @@ next-level-cache = <&L3_CA55_3>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; }; a55_7: cpu@30100 { @@ -134,6 +141,7 @@ next-level-cache = <&L3_CA55_3>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; }; L3_CA55_0: cache-controller-0 { From ea25b1836f57e91e2432b315727fc3f3b8c92872 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 8 Jun 2022 18:30:24 +0100 Subject: [PATCH 19/27] arm64: dts: renesas: rzg2ul-smarc: Enable RSPI1 on carrier board RSPI1 (SPI1) interface is available on PMOD0 connector (J1) on the carrier board. This patch adds pinmux and spi1 nodes to the carrier board dtsi file and drops deleting pinctl* properties from board DTS file. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220608173025.22792-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts | 6 ------ arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi | 7 +++++++ arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi | 6 ++++++ 3 files changed, 13 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts index 2d740bd420ca..121e55282d18 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts @@ -13,9 +13,3 @@ model = "Renesas SMARC EVK based on r9a07g043u11"; compatible = "renesas,smarc-evk", "renesas,r9a07g043u11", "renesas,r9a07g043"; }; - -&spi1 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi index 429bdde579c3..8fdc956cd6c7 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi @@ -209,6 +209,13 @@ pinmux = ; /* SD0_CD */ }; }; + + spi1_pins: rspi1 { + pinmux = , /* CK */ + , /* MOSI */ + , /* MISO */ + ; /* SSL */ + }; }; #if (SW_SW0_DEV_SEL) diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi index 0051634d7b1c..f9835c12023e 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi @@ -51,6 +51,12 @@ status = "disabled"; }; +&spi1 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + &ssi1 { /delete-property/ pinctrl-0; /delete-property/ pinctrl-names; From 52271d32348e22e5a7ce4fc80015ffb06a4ebf20 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 8 Jun 2022 18:30:25 +0100 Subject: [PATCH 20/27] arm64: dts: renesas: rzg2ul-smarc-som: Enable ADC on SMARC platform Enable the ADC found on RZ/G2UL SMARC SoM. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220608173025.22792-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi index 8fdc956cd6c7..cf3b3d118ef1 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi @@ -57,6 +57,14 @@ #endif }; +#if (SW_SW0_DEV_SEL) +&adc { + pinctrl-0 = <&adc_pins>; + pinctrl-names = "default"; + status = "okay"; +}; +#endif + #if (!SW_ET0_EN_N) ð0 { pinctrl-0 = <ð0_pins>; @@ -124,6 +132,10 @@ }; &pinctrl { + adc_pins: adc { + pinmux = ; /* ADC_TRG */ + }; + eth0_pins: eth0 { pinmux = , /* ET0_LINKSTA */ , /* ET0_MDC */ From 86aefa0d8dfa6dd488e2810461f714dd2794b0ee Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= Date: Wed, 8 Jun 2022 19:57:28 +0200 Subject: [PATCH 21/27] arm64: dts: renesas: Add missing space after remote-endpoint MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the missing space after remote-endpoint in r8a774c0.dtsi and r8a77990.dtsi before the typo spreads to other files. Signed-off-by: Niklas Söderlund Link: https://lore.kernel.org/r/20220608175728.1012550-1-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 4 ++-- arch/arm64/boot/dts/renesas/r8a77990.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index b6aeb22e8836..90588bbff7e0 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -1281,7 +1281,7 @@ vin4csi40: endpoint@2 { reg = <2>; - remote-endpoint= <&csi40vin4>; + remote-endpoint = <&csi40vin4>; }; }; }; @@ -1309,7 +1309,7 @@ vin5csi40: endpoint@2 { reg = <2>; - remote-endpoint= <&csi40vin5>; + remote-endpoint = <&csi40vin5>; }; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index d33021202637..4c7c7feed702 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -1324,7 +1324,7 @@ vin4csi40: endpoint@2 { reg = <2>; - remote-endpoint= <&csi40vin4>; + remote-endpoint = <&csi40vin4>; }; }; }; @@ -1352,7 +1352,7 @@ vin5csi40: endpoint@2 { reg = <2>; - remote-endpoint= <&csi40vin5>; + remote-endpoint = <&csi40vin5>; }; }; }; From c62872a6893ffdc38890b00d98d6bab2fce81d2f Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Mon, 13 Jun 2022 15:49:12 +0200 Subject: [PATCH 22/27] arm64: dts: renesas: r8a779f0: Add DMA properties to SCIF3 Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20220613134914.18655-1-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index 907984d2b81e..c0e4a1b1704d 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -457,6 +457,9 @@ <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x57>, <&dmac0 0x56>, + <&dmac1 0x57>, <&dmac1 0x56>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 704>; status = "disabled"; From 01a787f78bfd156d61b1844155f1dc4910e446c0 Mon Sep 17 00:00:00 2001 From: Linh Phung Date: Tue, 14 Jun 2022 11:51:09 +0200 Subject: [PATCH 23/27] arm64: dts: renesas: r8a779f0: Add HSCIF nodes Extracted from a bigger patch in the BSP, rebased and DMA properties added. Signed-off-by: Linh Phung Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20220614095109.8175-1-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 68 +++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index c0e4a1b1704d..3852bd150ff2 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -436,6 +436,74 @@ status = "disabled"; }; + hscif0: serial@e6540000 { + compatible = "renesas,hscif-r8a779f0", + "renesas,rcar-gen4-hscif", "renesas,hscif"; + reg = <0 0xe6540000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 514>, + <&cpg CPG_CORE R8A779F0_CLK_S0D3>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x31>, <&dmac0 0x30>, + <&dmac1 0x31>, <&dmac1 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 514>; + status = "disabled"; + }; + + hscif1: serial@e6550000 { + compatible = "renesas,hscif-r8a779f0", + "renesas,rcar-gen4-hscif", "renesas,hscif"; + reg = <0 0xe6550000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 515>, + <&cpg CPG_CORE R8A779F0_CLK_S0D3>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x33>, <&dmac0 0x32>, + <&dmac1 0x33>, <&dmac1 0x32>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 515>; + status = "disabled"; + }; + + hscif2: serial@e6560000 { + compatible = "renesas,hscif-r8a779f0", + "renesas,rcar-gen4-hscif", "renesas,hscif"; + reg = <0 0xe6560000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 516>, + <&cpg CPG_CORE R8A779F0_CLK_S0D3>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x35>, <&dmac0 0x34>, + <&dmac1 0x35>, <&dmac1 0x34>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 516>; + status = "disabled"; + }; + + hscif3: serial@e66a0000 { + compatible = "renesas,hscif-r8a779f0", + "renesas,rcar-gen4-hscif", "renesas,hscif"; + reg = <0 0xe66a0000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 517>, + <&cpg CPG_CORE R8A779F0_CLK_S0D3>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x37>, <&dmac0 0x36>, + <&dmac1 0x37>, <&dmac1 0x36>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 517>; + status = "disabled"; + }; + ufs: ufs@e6860000 { compatible = "renesas,r8a779f0-ufs"; reg = <0 0xe6860000 0 0x100>; From 40753144256b63b4e3fb9d80874605dda16ad713 Mon Sep 17 00:00:00 2001 From: Linh Phung Date: Tue, 14 Jun 2022 11:52:42 +0200 Subject: [PATCH 24/27] arm64: dts: renesas: r8a779f0: Add SCIF nodes Extracted from a bigger patch in the BSP, rebased, reg length corrected, and DMA properties added. Signed-off-by: Linh Phung Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20220614095242.8264-1-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 51 +++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index 3852bd150ff2..384817ffa4de 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -516,6 +516,40 @@ status = "disabled"; }; + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a779f0", + "renesas,rcar-gen4-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 702>, + <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x51>, <&dmac0 0x50>, + <&dmac1 0x51>, <&dmac1 0x50>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 702>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a779f0", + "renesas,rcar-gen4-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>, + <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x53>, <&dmac0 0x52>, + <&dmac1 0x53>, <&dmac1 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + }; + scif3: serial@e6c50000 { compatible = "renesas,scif-r8a779f0", "renesas,rcar-gen4-scif", "renesas,scif"; @@ -533,6 +567,23 @@ status = "disabled"; }; + scif4: serial@e6c40000 { + compatible = "renesas,scif-r8a779f0", + "renesas,rcar-gen4-scif", "renesas,scif"; + reg = <0 0xe6c40000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 705>, + <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x59>, <&dmac0 0x58>, + <&dmac1 0x59>, <&dmac1 0x58>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 705>; + status = "disabled"; + }; + dmac0: dma-controller@e7350000 { compatible = "renesas,dmac-r8a779f0", "renesas,rcar-gen4-dmac"; From 1614c8624a48b9c9161b2071e9e727bf5a1817ef Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Tue, 14 Jun 2022 21:30:05 +0200 Subject: [PATCH 25/27] arm64: dts: renesas: spider-cpu: Enable SCIF0 on second connector The schematics label it as SCIF0 debug port. Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20220614193005.2652-1-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- .../arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi | 13 +++++++++++++ arch/arm64/boot/dts/renesas/r8a779f0-spider.dts | 1 + 2 files changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi index 41aa8591b3b1..81d178e69527 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi @@ -60,6 +60,11 @@ function = "scif3"; }; + scif0_pins: scif0 { + groups = "scif0_data", "scif0_ctrl"; + function = "scif0"; + }; + scif_clk_pins: scif_clk { groups = "scif_clk"; function = "scif_clk"; @@ -79,6 +84,14 @@ status = "okay"; }; +&scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + status = "okay"; +}; + &scif_clk { clock-frequency = <24000000>; }; diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts b/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts index 2e3b719cc749..7a7c8ffba711 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts @@ -15,6 +15,7 @@ aliases { serial0 = &scif3; + serial1 = &scif0; }; chosen { From 62e8a53431145e06e503b71625a34eaa87b72b2c Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 15 Jun 2022 16:04:26 +0200 Subject: [PATCH 26/27] arm64: dts: renesas: Fix thermal-sensors on single-zone sensors MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit "make dtbs_check": arch/arm64/boot/dts/renesas/r8a774c0-cat874.dtb: thermal-zones: cpu-thermal:thermal-sensors: [[74], [0]] is too long arch/arm64/boot/dts/renesas/r8a774c0-ek874.dtb: thermal-zones: cpu-thermal:thermal-sensors: [[79], [0]] is too long arch/arm64/boot/dts/renesas/r8a774c0-ek874-idk-2121wr.dtb: thermal-zones: cpu-thermal:thermal-sensors: [[82], [0]] is too long arch/arm64/boot/dts/renesas/r8a774c0-ek874-mipi-2.1.dtb: thermal-zones: cpu-thermal:thermal-sensors: [[87], [0]] is too long arch/arm64/boot/dts/renesas/r8a77990-ebisu.dtb: thermal-zones: cpu-thermal:thermal-sensors: [[105], [0]] is too long From schema: Documentation/devicetree/bindings/thermal/thermal-zones.yaml Indeed, the thermal sensors on R-Car E3 and RZ/G2E support only a single zone, hence #thermal-sensor-cells = <0>. Fix this by dropping the bogus zero cell from the thermal sensor specifiers. Fixes: 8fa7d18f9ee2dc20 ("arm64: dts: renesas: r8a77990: Create thermal zone to support IPA") Fixes: 8438bfda9d768157 ("arm64: dts: renesas: r8a774c0: Create thermal zone to support IPA") Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Link: https://lore.kernel.org/r/28b812fdd1fc3698311fac984ab8b91d3d655c1c.1655301684.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a77990.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 90588bbff7e0..c563d26a7a71 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -1952,7 +1952,7 @@ cpu-thermal { polling-delay-passive = <250>; polling-delay = <0>; - thermal-sensors = <&thermal 0>; + thermal-sensors = <&thermal>; sustainable-power = <717>; cooling-maps { diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 4c7c7feed702..565e9d85946e 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -2129,7 +2129,7 @@ cpu-thermal { polling-delay-passive = <250>; polling-delay = <0>; - thermal-sensors = <&thermal 0>; + thermal-sensors = <&thermal>; sustainable-power = <717>; cooling-maps { From 3c7742a45c170430001c5a1767d9dd76686dc14d Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 15 Jun 2022 16:01:10 +0200 Subject: [PATCH 27/27] ARM: dts: rza2mevb: Fix LED node names "make dtbs_check": arch/arm/boot/dts/r7s9210-rza2mevb.dtb: leds: 'green', 'red' do not match any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/leds/leds-gpio.yaml Fix this by prefixing the LED node names with "led-". Signed-off-by: Geert Uytterhoeven Reviewed-by: Kieran Bingham Link: https://lore.kernel.org/r/f6e2883c16803b5d90a26c38d8e61ad15096089c.1655301593.git.geert+renesas@glider.be --- arch/arm/boot/dts/r7s9210-rza2mevb.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/r7s9210-rza2mevb.dts b/arch/arm/boot/dts/r7s9210-rza2mevb.dts index 9c0d9686fe01..69a5a44b8a2f 100644 --- a/arch/arm/boot/dts/r7s9210-rza2mevb.dts +++ b/arch/arm/boot/dts/r7s9210-rza2mevb.dts @@ -71,10 +71,10 @@ leds { compatible = "gpio-leds"; - red { + led-red { gpios = <&pinctrl RZA2_PIN(PORT6, 0) GPIO_ACTIVE_HIGH>; }; - green { + led-green { gpios = <&pinctrl RZA2_PIN(PORTC, 1) GPIO_ACTIVE_HIGH>; }; };