OMAP3 clock: only unlock SDRC DLL if SDRC clk < 83MHz

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According to the 34xx TRM Rev. K section 11.2.4.4.11.1 "Purpose of the
DLL/CDL Module," the SDRC delay-locked-loop can be locked at any SDRC
clock frequency from 83MHz to 166MHz.  CDP code unconditionally
unlocked the DLL whenever shifting to a lower SDRC speed, but this
seems unnecessary and error-prone, as the DLL is no longer able to
compensate for process, voltage, and temperature variations.  Instead,
only unlock the DLL when the SDRC clock rate would be less than 83MHz.

Signed-off-by: Paul Walmsley <paul@pwsan.com>

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Paul Walmsley 2009-05-12 17:26:32 -06:00 • committed by paul

parent b2abb271a5

commit 4519c2bf43

4 changed files with 24 additions and 12 deletions

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10

arch/arm/mach-omap2/clock34xx.c

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13

arch/arm/mach-omap2/sram34xx.S

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6

arch/arm/plat-omap/include/mach/sram.h

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7

arch/arm/plat-omap/sram.c

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