intel-pinctrl fixes for v5.4 part 2

A couple more fixes for Intel pinctrl drivers:
 
   - Try to avoid glitches when pin is in GPIO mode
   - Fix cherryview irq_valid_mask calculation
   - Allocate cherryview IRQ chip dynamically to avoid triggering warning
     from GPIO core
 -----BEGIN PGP SIGNATURE-----
 
 iQJUBAABCgA+FiEEVTdhRGBbNzLrSUBaAP2fSd+ZWKAFAl24fLkgHG1pa2Eud2Vz
 dGVyYmVyZ0BsaW51eC5pbnRlbC5jb20ACgkQAP2fSd+ZWKD0QxAAjyg4YGZ9kZD4
 MztOOG/l8T+qPRvqg0vWg5yQCP8zcRA15kZ9ybMGHIl4nBPQ2sjfEd5Eu1iArUYt
 ieM/T4VJrnCAGJdwj522vLhEfAuaiymq8cAv1DcAk0bVTr/UF32KF5Pq9ZGAReHC
 MlkOXMOmihBZ7Oyc9ZMSP+yN122+TvLHmMREbigzyukwtCSNpIUjdu9g+qDRlM/e
 agxrN9sGPdLt/xQmPHrJwZ66Y1lHl4LkQIxRadr/3oLyg0u6fCkfB3IdXrL2qM+E
 QycJ1NjEgFQMJEJZGxL9jPVS4vzmH9B4oFAS8mAaqUyOi9LvTANKm/mdkYjtdfjC
 9e4H+ReneSdtglH2m5fQ3I6zehuBGVbKHfdcLupYWLOyQ4uOepx8F8JgYDLXOSlS
 1u0DGmxT4TS6+rbKlo05QVLS1xqRbkSgBUmxNTc84zEgnRDyyz4GFGM3ANWksX0a
 cATYOK2XViPGGFv733IRdy4rGGkYpV7T8nq/N0Pj12e+cPo27OiE93ouHrgi6Ovb
 4OEbZPSTMwBQ46lZ9io3IEkMwSeN9AbO0u4+9zbN3sKZM89uzMnJeb4IPeUfGLVc
 d691Bb1TtSVqtZuXr0Y4d4ou3D3s1AwICHQ3+4dmX2992dJUZyAAJB67fqzb9gbF
 VWLyWdKCu/nl+BT5QYU5t7S0BzdpCQs=
 =3AVf
 -----END PGP SIGNATURE-----

Merge tag 'intel-pinctrl-fixes-v5.4-2' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into fixes

intel-pinctrl fixes for v5.4 part 2

A couple more fixes for Intel pinctrl drivers:

  - Try to avoid glitches when pin is in GPIO mode
  - Fix cherryview irq_valid_mask calculation
  - Allocate cherryview IRQ chip dynamically to avoid triggering warning
    from GPIO core
This commit is contained in:
Linus Walleij 2019-10-30 10:32:55 +01:00
commit 451a59bd1f
2 changed files with 33 additions and 14 deletions