drm/i915: panel power sequencing for VLV eDP v2

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PPS register offsets have changed in Valleyview.

v2: don't clobber port select bits on VLV when fixing up PPS timings
    don't bother with G4x PPS regs (Jani)

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

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Jesse Barnes 2013-03-28 09:55:41 -07:00 • committed by Daniel Vetter

parent b2634017b2

commit 453c542059

2 changed files with 131 additions and 51 deletions

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9

drivers/gpu/drm/i915/i915_reg.h

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173

drivers/gpu/drm/i915/intel_dp.c

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