drm/amd/display: Fix writeback completion timing

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[WHY]
The out fence was signalled on the first vblank after arming, before the
DMA finished copying, and the old code worked around this with an
mdelay() in the IRQ handler.

[HOW]
Hold a vblank reference while writeback is pending and signal the out
fence on the second vblank instead of using mdelay(). Add
amdgpu_dm_crtc_complete_writeback() to finish and clean up writeback
from both the IRQ and teardown paths.

This can be verified by running IGT's kms_writeback 20 times without
timeout errors.

Assisted-by: Copilot:Claude-Opus-4.8
Signed-off-by: Alex Hung <alex.hung@amd.com>
Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

This commit is contained in:

Alex Hung 2026-07-10 21:31:58 -06:00 • committed by Alex Deucher

parent 1d8cfeb69d

commit 459e61b539

3 changed files with 21 additions and 15 deletions

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1

drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h

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2

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

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33

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

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