drm/amd/display: Set disp clk in a safe way to avoid over high dpp clk. (v2)

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Increase clock, if current dpp div is 0 and request dpp div is 1, request clk is
higher than maximum dpp clk as per dpm table.
	set dispclk to the value of maximum supported dpp clk
	set div to 1
	set dispclk to request value.
Decrease clock, currrent dpp div is 1 and request dpp div is 0, current clk is
higher than maximum dpp clk as per dpm table.
	set dispclk to the value of maximum supported dpp clk
	set div to 0
	set dispclk to request value.

v2: squash in !DCN build fix

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

This commit is contained in:

Yongqiang Sun 2018-02-28 17:14:50 -05:00 • committed by Alex Deucher

parent 5231f5d112

commit 45bb8dd696

3 changed files with 139 additions and 23 deletions

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19

drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c

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1

drivers/gpu/drm/amd/display/dc/dc.h

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142

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

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