clk: samsung: exynos5420: Add SET_RATE_PARENT flag to clocks on G3D path

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Add CLK_SET_RATE_PARENT flag to all clocks on the path from VPLL to G3D,
so the G3D MALI driver can simply adjust the rate of its clock by doing
a single clk_set_rate() call, without the need to know the whole clock
topology in Exynos542x SoCs.

Suggested-by: Marian Mihailescu <mihailescu2m@gmail.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

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Marek Szyprowski 2019-10-25 11:34:35 +02:00 • committed by Sylwester Nawrocki

parent e21be0d1d7

commit 45f10dabb5

1 changed files with 12 additions and 8 deletions

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drivers/clk/samsung/clk-exynos5420.c

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