drm/i915/display: Add compare config for MTL+ platforms

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Currently, we may bump into pll mismatch errors during the
state verification stage. This happens when we try to use
fastset instead of full modeset. Hence, we would need to add
a check for pipe configuration to ensure that the sw and the
hw configuration will match. In case of hw and sw mismatch,
we would need to disable fastset and use full modeset instead.

v2: Fix C10 error on PLL comparison (BAT)
    Use memcmp instead of fixed loops for pll config
    comparison (Jani)
    Clean up and use intel_cx0pll_dump_hw_state() to dump
    pll information (Jani)

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240523134649.31452-3-mika.kahola@intel.com

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This commit is contained in:

Mika Kahola 2024-05-23 16:46:49 +03:00

parent 5575d7b661

commit 45fe957ae7

4 changed files with 109 additions and 10 deletions

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77

drivers/gpu/drm/i915/display/intel_cx0_phy.c

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8

drivers/gpu/drm/i915/display/intel_cx0_phy.h

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33

drivers/gpu/drm/i915/display/intel_display.c

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1

drivers/gpu/drm/i915/display/intel_dpll_mgr.h

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