drm/i915/color: Fix step discontinuity in Post-CSC Gamma LUT

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Fix a step discontinuity in the Post-CSC Gamma LUT when SDR dimming
is active by clamping Segment 2 to the last user-provided LUT entry
value instead of hardcoding it to 1.0 (1 << 24).

Link: https://lore.kernel.org/intel-gfx/20260521180143.2143262-1-sean@poorly.run/ #v1
Link: https://lore.kernel.org/intel-gfx/20260525135730.1122696-1-sean@poorly.run/ #v2

Changes in v2:
- Split out into separate patches for pre/post csc fixes
- Dropped loop bounds fix in favor of [1]
Changes in v3:
- None

[1]- https://lore.kernel.org/r/20260519075245.383864-1-pranay.samala@intel.com

Signed-off-by: Sean Paul <seanpaul@google.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patch.msgid.link/20260528230817.2455072-1-sean@poorly.run

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Sean Paul 2026-05-28 19:07:46 -04:00 • committed by Uma Shankar

parent c6eea19251

commit 466a751e17

1 changed files with 2 additions and 2 deletions

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drivers/gpu/drm/i915/display/intel_color.c

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