drm/i915: Don't set a MBZ bit in gen2/3 MI_FLUSH

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On gen2 MI_EXE_FLUSH is actually an AGP flush bit and on gen3 marked as
reserved.  On both it is documented as being must-be-zero. So obey the
documentation, and separate the gen2 flush into its own little routine
and share with gen3.

This means that we can rename the existing render_ring_flush() to
reflect the generation from which it first applies and remove the code
for handling earlier generations from it.

v2: Applies to gen3 as well
v3: Make it compile and improve the commit message.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

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Chris Wilson 2012-04-18 11:12:11 +01:00 • committed by Daniel Vetter

parent 6b8e6ed02a

commit 46f0f8d120

1 changed files with 39 additions and 16 deletions

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drivers/gpu/drm/i915/intel_ringbuffer.c

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